Motor de Búsqueda de Datasheet de Componentes Electrónicos
  Spanish  ▼
ALLDATASHEET.ES

X  

TLC32045CN Datasheet(PDF) 4 Page - Texas Instruments

No. de pieza TLC32045CN
Descripción Electrónicos  VOICE-BAND ANALOG INTERFACE CIRCUITS
Download  39 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Fabricante Electrónico  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
Logo TI1 - Texas Instruments

TLC32045CN Datasheet(HTML) 4 Page - Texas Instruments

  TLC32045CN Datasheet HTML 1Page - Texas Instruments TLC32045CN Datasheet HTML 2Page - Texas Instruments TLC32045CN Datasheet HTML 3Page - Texas Instruments TLC32045CN Datasheet HTML 4Page - Texas Instruments TLC32045CN Datasheet HTML 5Page - Texas Instruments TLC32045CN Datasheet HTML 6Page - Texas Instruments TLC32045CN Datasheet HTML 7Page - Texas Instruments TLC32045CN Datasheet HTML 8Page - Texas Instruments TLC32045CN Datasheet HTML 9Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 4 / 39 page
background image
TLC32044C, TLC32044E, TLC32044I, TLC32044M, TLC32045C, TLC32045I
VOICE-BAND ANALOG INTERFACE CIRCUITS
SLAS017F − MARCH 1988 − REVISED MAY 1995
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions (continued)
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
EODX
11
O
End of data transmit. (See the WORD/BYTE description and Serial Port Timing diagram.) During the
word-mode timing, EODX is a low-going pulse that occurs immediately after the 16 bits of D/A converter
and control or register information have been transmitted from the TMS320 (SMJ320) serial port to the AIC.
EODX can be used to interrupt a microprocessor upon the completion of serial communications. Also,
EODX can be used to strobe and enable external serial-to-parallel shift registers, latches, or an external
FIFO RAM, and to facilitate parallel data-bus communications between the AIC and the serial-to-parallel
shift registers. During the byte-mode timing, EODX goes low after the first byte has been transmitted from
the TMS320 (SMJ320) serial port to the AIC and is kept low until the second byte has been transmitted. The
DSP can use this low-going signal to differentiate between the two bytes as to which is first and which is
second.
FSR
4
O
Frame sync receive. In the serial transmission modes, which are described in the WORD/BYTE description,
FSR is held low during bit transmission. When FSR goes low, the TMS320 (SMJ320) serial port begins
receiving bits from the AIC via DR of the AIC. The most significant DR bit is present on DR before FSR goes
low. (See Serial Port Timing and Internal Timing Configuration diagrams.) FSR does not occur after
secondary communications.
FSX
14
O
Frame sync transmit. When FSX goes low, the TMS320 (SMJ320) serial port begins transmitting bits to the
FSX
14
O
Frame sync transmit. When FSX goes low, the TMS320 (SMJ320) serial port begins transmitting bits to the
AIC via DX of the AIC. In all serial transmission modes, which are described in the WORD/BYTE description,
FSX is held low during bit transmission (see Serial Port Timing and Internal Timing Configuration diagrams).
AIC via DX of the AIC. In all serial transmission modes, which are described in the WORD/BYTE description,
FSX is held low during bit transmission (see Serial Port Timing and Internal Timing Configuration diagrams).
IN +
26
I
Noninverting input to analog input amplifier stage
IN −
25
I
Inverting input to analog input amplifier stage
MSTR CLK
6
I
Master clock. MSTR CLK is used to derive all the key logic signals of the AIC, such as the shift clock, the
switched-capacitor filter clocks, and the A/D and D/A timing signals. The Internal Timing Configuration
diagram shows how these key signals are derived. The frequencies of these key signals are synchronous
submultiples of the master clock frequency to eliminate unwanted aliasing when the sampled analog signals
are transferred between the switched-capacitor filters and the A/D and D/A converters (see the Internal
Timing Configuration diagram).
OUT +
22
O
Noninverting output of analog output power amplifier. OUT+ can drive transformer hybrids or
high-impedance loads directly in either a differential or a single-ended configuration.
OUT −
21
O
Inverting output of analog output power amplifier. OUT− is functionally identical with and complementary
to OUT +.
REF
8
I/O
Internal voltage reference. An internal reference voltage is brought out on REF. An external voltage
reference can also be applied to REF.
RESET
2
I
Reset function. RESET is provided to initialize the TA, TA’, TB, RA, RA’, RB, and control registers. A reset
initiates serial communications between the AIC and DSP. A reset initializes all AIC registers including the
control register. After a negative-going pulse on RESET, the AIC registers are initialized to provide an 8-khz
data conversion rate for a 5.184-MHz master clock input signal. The conversion rate adjust registers, TA’
and RA’, are reset to 1. The control register bits are reset as follows (see AIC DX data word format section):
d9 = 1, d7 = 1, d6 = 1, d5 = 1, d4 = 0, d3 = 0, d2 = 1.
This initialization allows normal serial-port communication to occur between the AIC and DSP.
SHIFT CLK
10
O
Shift clock. SHIFT CLK is obtained by dividing the master clock signal frequency by four. SHIFT CLK is used
to clock the serial data transfers of the AIC, described in the WORD/BYTE description below (see the Serial
Port Timing and Internal Timing Configuration diagrams).
VDD
7
Digital supply voltage, 5 V
±5%
VCC +
20
Positive analog supply voltage, 5 V
±5%
VCC −
19
Negative analog supply voltage, − 5 V
±5%


Número de pieza similar - TLC32045CN

Fabricante ElectrónicoNo. de piezaDatasheetDescripción Electrónicos
logo
Texas Instruments
TLC32045CN TI-TLC32045CN Datasheet
535Kb / 39P
[Old version datasheet]   VOICE-BAND ANALOG INTERFACE CIRCUITS
TLC32045CN TI1-TLC32045CN Datasheet
528Kb / 39P
[Old version datasheet]   VOICE-BAND ANALOG INTERFACE CIRCUITS
More results

Descripción similar - TLC32045CN

Fabricante ElectrónicoNo. de piezaDatasheetDescripción Electrónicos
logo
Texas Instruments
TLC32044MJB TI1-TLC32044MJB Datasheet
512Kb / 39P
[Old version datasheet]   VOICE-BAND ANALOG INTERFACE CIRCUITS
TLC32044C TI-TLC32044C Datasheet
535Kb / 39P
[Old version datasheet]   VOICE-BAND ANALOG INTERFACE CIRCUITS
TLC32044C TI1-TLC32044C_11 Datasheet
528Kb / 39P
[Old version datasheet]   VOICE-BAND ANALOG INTERFACE CIRCUITS
TLC32046 TI1-TLC32046 Datasheet
273Kb / 56P
[Old version datasheet]   Wide-Band Analog Interface Circuit
TLC32046CFN TI-TLC32046CFN Datasheet
247Kb / 56P
[Old version datasheet]   Wide-Band Analog Interface Circuit
TLC32047C TI-TLC32047C Datasheet
303Kb / 61P
[Old version datasheet]   Wide-Band Analog Interface Circuit
TLC32040C TI-TLC32040C Datasheet
453Kb / 33P
[Old version datasheet]   ANALOG INTERFACE CIRCUITS
TLC32046C TI-TLC32046C Datasheet
297Kb / 57P
[Old version datasheet]   Wide-Band Analog Interface Circuit
logo
CML Microcircuits
FX004 CMLMICRO-FX004 Datasheet
338Kb / 9P
   Voice Band Inverter
MX004 CMLMICRO-MX004 Datasheet
370Kb / 9P
   VOICE BAND INVERTER
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39


Datasheet Descarga

Go To PDF Page


Enlace URL




Política de Privacidad
ALLDATASHEET.ES
¿ALLDATASHEET es útil para Ud.?  [ DONATE ] 

Todo acerca de Alldatasheet   |   Publicidad   |   Contáctenos   |   Política de Privacidad   |   Intercambio de Enlaces   |   Lista de Fabricantes
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com