TLC32044C, TLC32044E, TLC32044I, TLC32044M, TLC32045C, TLC32045I

VOICE-BAND ANALOG INTERFACE CIRCUITS

SLAS017F − MARCH 1988 − REVISED MAY 1995

5

POST OFFICE BOX 655303

Terminal Functions (continued)

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

WORD/BYTE

13

I

Used in conjunction with a bit in the control register, WORD/BYTE is used to establish one of four serial

modes. These four serial modes are described below.

AIC transmit and receive sections are operated asynchronously.

The following description applies when the AIC is configured to have asynchronous transmit and receive

sections. If the appropriate data bit in the control register is a 0 (see the AIC DX data word format section),

the transmit and receive sections are asynchronous.

L

Serial port directly interfaces with the serial port of the DSP and communicates in two

8-bit bytes. The operation sequence is as follows (see Serial Port Timing diagrams).

1. FSX or FSR is brought low.

2. One 8-bit byte is transmitted or one 8-bit byte is received.

3. EODX or EODR is brought low.

4. FSX or FSR emits a positive frame-sync pulse that is four shift clock cycles wide.

5. One 8-bit byte is transmitted or one 8-bit byte is received.

6. EODX or EODR is brought high.

7. FSX or FSR is brought high.

H

Serial port directly interfaces with the serial ports of the TMS(SMJ)32020, TMS(SMJ)320C25, or

TMS(SMJ)320C30, and communicates in one 16-bit word. The operation sequence is as follows

(see Serial Port Timing diagrams):

1.

FSX or FSR is brought low.

2. One 16-bit word is transmitted or one 16-bit word is received.

3. FSX or FSR is brought high.

4. EODX or EODR emits a low-going pulse.

AIC transmit and receive sections are operated synchronously.

If the appropriate data bit in the control register is 1, the transmit and receive sections are configured to be

synchronous. In this case, the bandpass switched-capacitor filter and the A/D conversion timing are derived

from the TX counter A, TX counter B, and TA, TA’, and TB registers, rather than the RX counter A, RX counter

B, and RA, RA’, and RB registers. In this case, the AIC FSX and FSR timing are identical during primary

data communication; however, FSR is not asserted during secondary data communication since there is

no new A/D conversion result. The synchronous operation sequences are as follows (see Serial Port Timing

diagrams).

L

Serial port directly interfaces with the serial port of the DSP and communicates in two 8-bit

bytes. The operation sequence is as follows (see Serial Port Timing diagrams):

1. FSX and FSR are brought low.

2. One 8-bit byte is transmitted and one 8-bit byte is received.

3. EODX and EODR are brought low.

4. FSX and FSR emit positive frame-sync pulses that are four shift clock cycles wide.

5. One 8-bit byte is transmitted and one 8-bit byte is received.

6. EODX and EODR are brought high.

7. FSX and FSR are brought high.

H

Serial port directly interfaces with the serial port of the TMS(SJM)32020, TMS(SMJ)320C25, or

TMS320C30, and communicates in one 16-bit word. The operation sequence is as follows (see

Serial Port Timing diagrams):

1. FSX and FSR are brought low.

2. One 16-bit word is transmitted and one 16-bit word is received.

3. FSX and FSR are brought high.

4. EODX or EODR emit low-going pulses.

Since the transmit and receive sections of the AIC are now synchronous, the AIC serial port with additional

NOR and AND gates interface to two SN74(54)299 serial-to-parallel shift registers. Interfacing the AIC to

the SN74(54)299 shift register allows the AIC to interface to an external FIFO RAM and facilitates parallel,

data bus communications between the AIC and the digital signal processor. The operation sequence is the

same as the above sequence (see Serial Port Timing diagrams).