CAT1161, CAT1162

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7

FUCTIONAL DESCRIPTION

protocol. This Inter−Integrated Circuit Bus protocol defines

any device that sends data to the bus to be a transmitter and

any device receiving data to be a receiver. The transfer is

controlled by the Master device which generates the serial

clock and all START and STOP conditions for bus access.

Both the Master device and Slave device can operate as

either transmitter or receiver, but the Master device controls

which mode is activated.

follows:

1. Data transfer may be initiated only when the bus is

not busy.

2. During a data transfer, the data line must remain

stable whenever the clock line is high. Any

changes in the data line while the clock line is high

will be interpreted as a START or STOP condition.

START Condition

The START Condition precedes all commands to the

device, and is defined as a HIGH to LOW transition of SDA

when SCL is HIGH. The CAT1161/2 monitors the SDA and

SCL lines and will not respond until this condition is met.

STOP Condition

A LOW to HIGH transition of SDA when SCL is HIGH

determines the STOP condition. All operations must end

with a STOP condition.

Device Addressing

The Master begins a transmission by sending a START

condition. The Master sends the address of the particular

slave device it is requesting. The four most significant bits

of the 8−bit slave address are fixed as 1010.

The next three bits (Figure 6) define memory addressing.

For the CAT1161/2 the three bits define higher order bits.

The last bit of the slave address specifies whether a Read

or Write operation is to be performed. When this bit is set to

1, a Read operation is selected, and when set to 0, a Write

operation is selected.

After the Master sends a START condition and the slave

address byte, the CAT1161/2 monitors the bus and responds

with an acknowledge (on the SDA line) when its address

matches the transmitted slave address. The CAT1161/2 then

performs a Read or Write operation depending on the

R/W bit.

Figure 5. Acknowledge Timing

ACKNOWLEDGE

1

RT

STA

SCL FROM

MASTER

8

DATA OUTPUT

FROM TRANSMITTER

DATA OUTPUT

FROM RECEIVER

9

Figure 6. Slave Address Bits

1

0

1

0

a10

a9

a8

R/W

Note: a8, a9 and a10 correspond to the address of the memory array address word.

CAT1161/2

Acknowledge

After a successful data transfer, each receiving device is

required to generate an acknowledge. The acknowledging

device pulls down the SDA line during the ninth clock cycle,

signaling that it received the 8 bits of data.

The CAT1161/2 responds with an acknowledge after

receiving a START condition and its slave address. If the

device has been selected along with a write operation, it

responds with an acknowledge after receiving each 8−bit

byte.

When the CAT1161/2 begins a READ mode it transmits

8 bits of data, releases the SDA line and monitors the line for

an acknowledge. Once it receives this acknowledge, the

CAT1161/2 will continue to transmit data. If no

acknowledge is sent by the Master, the device terminates

data transmission and waits for a STOP condition.