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AD7723BS Datasheet(PDF) 6 Page - Analog Devices |
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AD7723BS Datasheet(HTML) 6 Page - Analog Devices |
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6 / 32 page  AD7723 Rev. C | Page 6 of 32 TIMING SPECIFICATIONS AVDD = DVDD = 5 V ± 5%; AGND = AGND1 = DGND = 0 V; fCLKIN = 19.2 MHz; CL = 50 pF; SFMT = logic low or high, CFMT = logic low or high; TA = TMIN to TMAX, unless otherwise noted. Table 2. Parameter Symbol Min Typ Max Unit CLKIN Frequency fCLK 1 19.2 MHz CLKIN Period (tCLK – 1/fCLK) t1 0.052 1 µs CLKIN Low Pulse Width t2 0.45 × t1 0.55 × t1 CLKIN High Pulse Width t3 0.45 × t1 0.55 × t1 CLKIN Rise Time t4 5 ns CLKIN Fall Time t5 5 ns FSI Setup Time t6 0 5 ns FSI Hold Time t7 0 5 ns FSI High Time1 t8 1 tCLK CLKIN to SCO Delay t9 25 40 ns SCO Period2, SCR = 1 t10 2 tCLK SCO Period2, SCR = 0 t10 1 tCLK SCO Transition to FSO High Delay t11 0 5 ns SCO Transition to FSO Low Delay t12 0 5 ns SCO Transition to SDO Valid Delay t13 5 12 ns SCO Transition from FSI3 t14 60 tCLK + t2 SDO Enable Delay Time t15 5 20 ns SDO Disable Delay Time t16 5 20 ns DRDY High Time2 t17 2 tCLK Conversion Time2 (Refer to Table 3 and Table 4) t18 16/32 tCLK CLKIN to DRDY Transition t19 35 50 ns CLKIN to DATA Valid t20 20 35 ns CS/RD Setup Time to CLKIN t21 0 ns CS/RD Hold Time to CLKIN t22 20 ns Data Access Time t23 20 35 ns Bus Relinquish Time t24 20 35 ns SYNC Input Pulse Width t25 1 tCLK SYNC Low Time before CLKIN Rising t26 0 ns DRDY High Delay after Rising SYNC t27 25 35 ns DRDY Low Delay after SYNC Low t28 2049 tCLK 1 FSO pulses are gated by the release of FSI (going low). 2 Guaranteed by design. 3 Frame sync is initiated on the falling edge of CLKIN. IOL 1.6mA 1.6V CL 50pF TO OUTPUT PIN IOH 200 µA Figure 2. Load Circuit for Timing Specifications |
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