REV. G

–6–

AD7710

Parameter

(A, S Versions)

Unit

Conditions/Comments

External Clocking Mode

MHz max

Serial Clock Input Frequency

0

ns min

DRDY to RFS Setup Time

0

ns min

DRDY to RFS Hold Time

2

ns min

A0 to

RFS Setup Time

0

ns min

A0 to

RFS Hold Time

7

4

× t

CLK IN

ns max

Data Access Time (

RFS Low to Data Valid)

7

10

ns min

SCLK Falling Edge to Data Valid Delay

2

× t

ns max

2

× t

CLK IN

ns min

SCLK High Pulse Width

2

ns min

SCLK Low Pulse Width

ns max

SCLK Falling Edge to

DRDY High

8

10

ns min

SCLK to Data Valid Hold Time

ns max

10

ns min

RFS/TFS to SCLK Falling Edge Hold Time

8

5

× t

ns max

RFS to Data Valid Hold Time

0

ns min

A0 to

TFS Setup Time

0

ns min

A0 to

TFS Hold Time

4

× t

CLK IN

ns min

SCLK Falling Edge to

TFS Hold Time

2

ns min

Data Valid to SCLK Setup Time

30

ns min

Data Valid to SCLK Hold Time

NOTES

extrapolated back to remove effects of charging or discharging the 100 pF capacitor. This means that the times quoted in the timing characteristics are the true bus

relinquish times of the part and, as such, are independent of external bus loading capacitances.

Specifications subject to change without notice.

PIN CONFIGURATION

DIP AND SOIC

SCLK

MCLK IN

DGND

MODE

AIN1(+)

AGND

MCLK OUT

A0

SDATA

AIN1(–)

REF OUT

REF IN(+)

REF IN(–)

14

1

2

24

23

5

6

7

20

19

18

3

4

22

21

8

17

9

16

10

15

11

TOP VIEW

(Not to Scale)

11

12

13

AD7710

SYNC

DRDY

RFS

TFS

AIN2(+)

AIN2(–)

TO OUTPUT

PIN

+2.1V

1.6mA

200 A

100pF

Figure 1. Load Circuit for Access Time and

Bus Relinquish Time