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TPIC2801 Datasheet(PDF) 9 Page - Texas Instruments

No. de pieza TPIC2801
Descripción Electrónicos  OCTAL INTELLIGENT-POWER SWITCH WITH SERIAL INPUT
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Fabricante Electrónico  TI [Texas Instruments]
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TPIC2801
OCTAL INTELLIGENT POWER SWITCH
WITH SERIAL INPUT
SLIS008 − D3282, AUGUST 1989 − REVISED JUNE 1990
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
POST OFFICE BOX 1443
HOUSTON, TEXAS 77001
2−9
PARAMETER MEASUREMENT INFORMATION
GND
SO
Output
CL = 200 pF
(see Note A)
10 ns
10 ns
td1
tr(SO)
5 V
0
VOL
VOL
VOH
SCLK
Input
SO
Output
Waveform 1
(see Note B)
SO
Output
Waveform 2
(see Note B)
SCLK
tv
VOH
td1
tv
tf(SO)
VOLTAGE WAVEFORMS
TEST CIRCUIT FOR VALID DATA
DELAY TIME td1 AND VALID TIME tv
5 V
0.7 VCC
2.5 V
2.5 V
0.2 VCC
0.7 VCC
0.2 VCC
0.2 VCC
0.7 VCC
TPIC2801
Under
Test
VCC
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the low-to-high transition of SCLK causes the SO output to switch from
low to high. Waveform 2 is for an output with internal conditions such that the low-to-high transition of SCLK causes the SO output
to switch from high to low.
Figure 3. Test Circuit and Voltage Waveforms for Delay Times
TPIC2801
Under
Test
GND
Y
SIOE
RL = 5 Ω
Output
CL = 20 pF
(see Note A)
10 ns
90%
10%
10%
10 ns
50%
td2
5 V
0
Von = 5 V
IO(CL) = 1.2 A
0
SIOE
Input
Y-Output Voltage
(see Note B)
Y-Output Current
(see Note B)
11 V
90%
50%
Voff = 11 V
VOLTAGE WAVEFORMS
TEST CIRCUIT FOR UNLATCH DISABLE
DELAY TIME td2
(see Notes C and D)
5 V
2.5 V
2.5 V
VCC
NOTES: A. CL includes probe and jig capacitance.
B. Output voltage and current waveforms are for an output with internal conditions such that the low-to-high transition of SIOE causes
the output to switch from being off to being on.
C. td2 = delay until Y-output current goes off under fault condition.
D. Load voltage VS and load resistance RL are selected such that on-state voltage at the Y output under test, Von is greater than the
maximum out-of-saturation hold voltage, VTOS. Thus VOL = Von > VTOS(max) = 1.98 V.
Figure 4. Test Circuit and Voltage and Current Waveforms for Unlatch Disable Delay


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