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LM3S300-IQN25-C2 Datasheet(PDF) 11 Page - Texas Instruments |
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LM3S300-IQN25-C2 Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 498 page  List of Tables Table 1. Revision History .................................................................................................. 19 Table 2. Documentation Conventions ................................................................................ 24 Table 2-1. Summary of Processor Mode, Privilege Level, and Stack Use ................................ 45 Table 2-2. Processor Register Map ....................................................................................... 46 Table 2-3. PSR Register Combinations ................................................................................. 51 Table 2-4. Memory Map ....................................................................................................... 59 Table 2-5. Memory Access Behavior ..................................................................................... 61 Table 2-6. SRAM Memory Bit-Banding Regions .................................................................... 63 Table 2-7. Peripheral Memory Bit-Banding Regions ............................................................... 63 Table 2-8. Exception Types .................................................................................................. 69 Table 2-9. Interrupts ............................................................................................................ 70 Table 2-10. Exception Return Behavior ................................................................................... 74 Table 2-11. Faults ................................................................................................................. 75 Table 2-12. Fault Status and Fault Address Registers .............................................................. 76 Table 2-13. Cortex-M3 Instruction Summary ........................................................................... 78 Table 3-1. Core Peripheral Register Regions ......................................................................... 82 Table 3-2. Memory Attributes Summary ................................................................................ 85 Table 3-3. TEX, S, C, and B Bit Field Encoding ..................................................................... 88 Table 3-4. Cache Policy for Memory Attribute Encoding ......................................................... 89 Table 3-5. AP Bit Field Encoding .......................................................................................... 89 Table 3-6. Memory Region Attributes for Stellaris Microcontrollers .......................................... 89 Table 3-7. Peripherals Register Map ..................................................................................... 90 Table 3-8. Interrupt Priority Levels ...................................................................................... 109 Table 3-9. Example SIZE Field Values ................................................................................ 137 Table 4-1. JTAG_SWD_SWO Signals (48QFP) ................................................................... 141 Table 4-2. JTAG Port Pins Reset State ............................................................................... 142 Table 4-3. JTAG Instruction Register Commands ................................................................. 146 Table 5-1. System Control & Clocks Signals (48QFP) .......................................................... 150 Table 5-2. Reset Sources ................................................................................................... 151 Table 5-3. Clock Source Options ........................................................................................ 155 Table 5-4. Possible System Clock Frequencies Using the SYSDIV Field ............................... 156 Table 5-5. System Control Register Map ............................................................................. 160 Table 5-6. PLL Mode Control .............................................................................................. 172 Table 6-1. Flash Protection Policy Combinations ................................................................. 206 Table 6-2. Flash Register Map ............................................................................................ 210 Table 7-1. GPIO Pins With Non-Zero Reset Values .............................................................. 223 Table 7-2. GPIO Pins and Alternate Functions (48QFP) ....................................................... 223 Table 7-3. GPIO Signals (48QFP) ....................................................................................... 224 Table 7-4. GPIO Pad Configuration Examples ..................................................................... 228 Table 7-5. GPIO Interrupt Configuration Example ................................................................ 228 Table 7-6. GPIO Register Map ........................................................................................... 229 Table 8-1. Available CCP Pins ............................................................................................ 263 Table 8-2. General-Purpose Timers Signals (48QFP) ........................................................... 263 Table 8-3. 16-Bit Timer With Prescaler Configurations ......................................................... 266 Table 8-4. Timers Register Map .......................................................................................... 272 Table 9-1. Watchdog Timer Register Map ............................................................................ 300 11 June 18, 2012 Texas Instruments-Production Data Stellaris ® LM3S300 Microcontroller NRND: Not recommended for new designs. |
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