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FAN54040 Datasheet(PDF) 4 Page - Fairchild Semiconductor

No. de pieza FAN54040
Descripción Electrónicos  USB-OTG, 1.55 A, Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support
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Fabricante Electrónico  FAIRCHILD [Fairchild Semiconductor]
Página de inicio  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

FAN54040 Datasheet(HTML) 4 Page - Fairchild Semiconductor

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© 2012 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN54040
– FAN54047 • Rev. 1.0.2
4
Pin Configuration
Figure 3. Top View
Figure 4. Bottom View
Pin Definitions
Pin #
Name
Description
A1
SDA
I
2C Interface Serial Data. This pin should not be left floating.
B1
SCL
I
2C Interface Serial Clock. This pin should not be left floating.
C1
DIS
Disable. If this pin is held HIGH, Q1 and Q3 are turned off, creating a HIGH Z condition at VBUS and
the PWM converter is disabled.
D1
STAT
Status. Open-drain output indicating charge status. The IC pulls this pin LOW when charge is in
progress; can be used to signal the host processor when a fault condition occurs.
E1
POK_B
Power OK (FAN54040-2). Open-drain output that pulls LOW when VBUS is plugged in and the battery
has risen above VLOWV. This signal is used to signal the host processor that it can begin to draw
significant current.
E1
ILIM
Input Current Limit (FAN54045-7). Controls input current limit in Auto-Charge Mode. When LOW, input
current is limited to 100 mA maximum. When HIGH, input current is limited to 500 mA. In 32-Second
Mode, the input current limit is set by the IBUSLIM bits.
A2
– D2
PGND
Power Ground. Power return for gate drive and power transistors. The connection from this pin to the
bottom of CMID should be as short as possible.
E2
AGND
Analog Ground. All IC signals are referenced to this node.
A3
– C3
SW
Switching Node. Connect to output inductor.
D3
– E3
SYS
System Supply. Output voltage of the switching charger and input to the power path controller. Bypass
SYS to PGND with a 10
μF capacitor.
A4
– C4
PMID
Power Input Voltage. Power input to the charger regulator, bypass point for the input current sense.
Bypass with a minimum of a 4.7
F, 6.3 V capacitor to PGND.
D4
– E4
VBAT
Battery Voltage. Connect to the positive (+) terminal of the battery pack. Bypass with a 10
F capacitor
to PGND. VBAT is a power path connection.
A5
– B5
VBUS
Charger Input Voltage and USB-OTG output voltage. Bypass with a 1
F capacitor to PGND.
C5
GATE
External MOSFET Gate. This pin controls the gate of an external P-channel MOSFET transistor used to
augment the internal ideal diode. The source of the P-channel MOSFET should be connected to SYS
and the drain should be connected to VBAT.
D5
NTC
Thermistor input. The IC compares this node with taps on a resistor divider from REF to inhibit auto-
charging when the battery temperature is outside of permitted fast-charge limits.
E5
REF
Reference Voltage. REF is a 1.8 V regulated output.
REF
NTC
PGND
GATE
DIS
STAT
SCL
SDA
POK_B
SYS
VBAT
SW
PMID
VBUS
AGND
A1
A2
A3
A4
A5
B1
B3
B2
B4
B5
C1
C3
C2
C4
C5
D1
D3
D2
D4
D5
E1
E3
E2
E4
E5
C1
B1
A1
C5
B5
A5
A4
C4
D1
D5
D4
B4
E1
E5
E4
C3
B3
A3
A2
C2
D3
D2
B2
E3
E2


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