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74LVC2G17GM Datasheet(PDF) 1 Page - NXP Semiconductors

No. de pieza 74LVC2G17GM
Descripción Electrónicos  Dual non-inverting Schmitt trigger with 5 V tolerant input
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Fabricante Electrónico  NXP [NXP Semiconductors]
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74LVC2G17GM Datasheet(HTML) 1 Page - NXP Semiconductors

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1.
General description
The 74LVC2G17 provides two non-inverting buffers with Schmitt trigger input. It is capable
of transforming slowly changing input signals into sharply defined, jitter-free output
signals.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these
devices as translators in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using IOFF.
The IOFF circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
2.
Features and benefits
Wide supply voltage range from 1.65 V to 5.5 V
5 V tolerant input/output for interfacing with 5 V logic
High noise immunity
Complies with JEDEC standard:
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD-8B/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
24 mA output drive (V
CC =3.0 V)
CMOS low-power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Multiple package options
Specified from
40 Cto+85 C and 40 Cto+125 C
3.
Applications
Wave and pulse shapers for highly noisy environments
74LVC2G17
Dual non-inverting Schmitt trigger with 5 V tolerant input
Rev. 8 — 2 May 2013
Product data sheet


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