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AD538BD Datasheet(PDF) 11 Page - Analog Devices |
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AD538BD Datasheet(HTML) 11 Page - Analog Devices |
11 / 17 page AD538 Rev. E | Page 10 of 16 FUNCTIONAL DESCRIPTION As shown in Figure 1 and Figure 11, the VZ and VX inputs connect directly to the input log ratio amplifiers of the AD538. This subsection provides an output voltage proportional to the natural log of input voltage, VZ, minus the natural log of input voltage, VX. The output of the log ratio subsection at B can be expressed by the transfer function = X Z B V V q kT V ln where: k is 1.3806 × 10−23 J/K. q is 1.60219 × 10−19 C. T is in Kelvins. The log ratio configuration may be used alone, if correctly temperature compensated and scaled to the desired output level (see the Applications Information section). Under normal operation, the log-ratio output will be directly connected to a second functional block at Input C, the antilog subsection. This section performs the antilog according to the transfer function: = kT q V e V V C Y O As with the log-ratio circuit included in the AD538, the user may use the antilog subsection by itself. When both subsections are combined, the output at B is tied to C, the transfer function of the AD538 computational unit is: VO = VYe C B V V kT q Q kT V V X Z = ; ln which reduces to: = X Z Y O V V V V Finally, by increasing the gain, or attenuating the output of the log ratio subsection via resistor programming, it is possible to raise the quantity VZ/VX to the mth power. Without external programming, m is unity. Thus, the overall AD538 transfer function equals: m X Z Y O V V V V = where 0.2 < m < 5. When the AD538 is used as an analog divider, the VY input can be used to multiply the ratio VZ/VX by a convenient scale factor. The actual multiplication by the VY input signal is accomplished by adding the log of the VY input signal to the signal at C, which is already in the log domain. STABILITY PRECAUTIONS At higher frequencies, the multistaged signal path of the AD538 can result in large phase shifts (as illustrated in Figure 11). If a condition of high incremental gain exists along that path (for example, VO = VY × VZ/VX = 10 V × 10 mV/10 mV = 10 V so that ΔVO/ΔVX = 1000), then small amounts of capacitive feedback from VO to the current inputs IZ or IX can result in instability. Appropriate care should be exercised in board layout to prevent capacitive feedback mechanisms under these conditions. LOGe IY VY Ln Y LOGe IZ VZ Ln Z LOGe IX VX Ln X Σ Σ BUFFER + + + – Ln Z – Ln X M(Ln Z – Ln X) M(Ln Z – Ln X) +Ln Y ANTILOGe 0.2 ≤M≤5 VO = VY VZ VX M Figure 11. Model Circuit USING THE VOLTAGE REFERENCES A stable band gap voltage reference for scaling is included in the AD538. It is laser-trimmed to provide a selectable voltage output of +10 V buffered (Pin 4), +2 V unbuffered (Pin 5) or any voltages between +2 V and +10.2 V buffered as shown in Figure 12. The output impedance at Pin 5 is approximately 5 kΩ. Note that any loading of this pin produces an error in the +10 V reference voltage. External loads on the +2 V output should be greater than 500 kΩ to maintain errors less than 1%. 25k Ω 25k Ω 100 Ω 25k Ω 25k Ω ANTILOG LOG OUTPUT 100 Ω 50k Ω +2V TO +10.2V BUFFERED 11.5k Ω AD538 IY A D IX VX C VY 8 1 1 17 16 15 14 13 12 11 10 2 3 4 5 6 7 8 9 LOG RATIO INTERNAL VOLTAGE REFERENCE SIGNAL GND PWR GND IZ VZ VO I +VS –VS B REF OUT +2V Figure 12. +2 V to +10.2 V Adjustable Reference In situations not requiring both reference levels, the +2 V output can be converted to a buffered output by tying Pin 4 and Pin 5 together. If both references are required simultaneously, the +10 V output should be used directly and the +2 V output should be externally buffered. |
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