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AD713JR-16-REEL Datasheet(PDF) 11 Page - Analog Devices |
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AD713JR-16-REEL Datasheet(HTML) 11 Page - Analog Devices |
11 / 20 page AD713 Rev. F | Page 11 of 20 THEORY OF OPERATION MEASURING AD713 SETTLING TIME The error signal is thus clamped twice: once to prevent overload- ing amplifier A2 and then a second time to avoid overloading the oscilloscope preamp. A Tektronix oscilloscope preamp Type 7A26 was carefully chosen because it recovers from the approximately 0.4 V overload quickly enough to allow accurate measurement of the AD713 1 μs settling time. Amplifier A2 is a very high speed FET input op amp; it provides a voltage gain of 10, amplifying the error signal output of the AD713 under test (providing an overall gain of 5). Figure 30 and Figure 31 show the dynamic response of the AD713 while operating in the settling time test circuit of Figure 29. The input of the settling time fixture is driven by a flat-top pulse generator. The error signal output from the false summing node of A1, the AD713 under test, is clamped, amplified by Op Amp A2, and then clamped again. 10kΩ 200Ω 4.99kΩ 10kΩ 4.99kΩ 5pF TO 18pF +VS –VS VIN + + 10pF 0.1µF 0.1µF 1µF 1µF 5kΩ 1/4 AD713 A1 4 11 + A2 5pF + 0.2pF TO 0.8pF 10kΩ 206Ω 2 × HP2835 2 × HP2835 1.1kΩ +VS –VS 0.47µF 0.47µF VERROR × 5 * FLAT-TOP PULSE GENERATOR DATA DYNAMICS 5109 OR EQUIVALENT *USE VERY SHORT CABLE OR TERMINATION RESISTOR NOTES 1. USE CIRCUIT BOARD WITH GROUND PLANE. TO TEKTRONIX 7A26 OSCILLOSCOPE PREAMP INPUT SECTION (VIA LESS THAN 1FT 50Ω COAXIAL CABLE) 20pF 1MΩ •• • • • • • • • •• • • •• • • •• • • •• • • •• • • •• • • •• • • •• • •• • • • • • • • •• • • •• • • •• • • •• • • •• • • •• • • •• • • •• • 100 90 10 0% 5mV 5V 500ns Figure 31. Settling Characteristics to –10 V Step, Upper Trace: Output of AD713 Under Test (5 V/div), Lower Trace: Amplified Error Voltage (0.01%/div) POWER SUPPLY BYPASSING The power supply connections to the AD713 must maintain a low impedance to ground over a bandwidth of 4 MHz or more. This is especially important when driving a significant resistive or capacitive load because all current delivered to the load comes from the power supplies. Multiple high quality bypass capacitors are recommended for each power supply line in any critical application. As shown in Figure 32, a 0.1 μF ceramic and a 1 μF electrolytic capacitor placed as close as possible to the amplifier (with short lead lengths to power supply common) assures adequate high frequency bypassing in most applications. A minimum bypass capacitance of 0.1 μF should be used for any application. Figure 29. Settling Time Test Circuit •• • • • • • • • •• • • •• • • •• • • •• • • •• • • •• • • •• • • •• • •• • • • • • • • •• • • •• • • •• • • •• • • •• • • •• • • •• • • •• • 100 90 10 0% 5mV 5V 500ns +VS –VS 1/4 AD713 4 11 + 1µF 0.1µF + 1µF 0.1µF Figure 32. Recommended Power Supply Bypassing Figure 30. Settling Characteristics 0 V to 10 V Step, Upper Trace: Output of AD713 Under Test (5 V/div), Lower Trace: Amplified Error Voltage (0.01%/div) |
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