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AD9559PCBZ Datasheet(PDF) 5 Page - Analog Devices |
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AD9559PCBZ Datasheet(HTML) 5 Page - Analog Devices |
5 / 120 page Data Sheet AD9559 Rev. 0 | Page 5 of 120 POWER DISSIPATION Table 3. Parameter Min Typ Max Unit Test Conditions/Comments POWER DISSIPATION Typical Configuration 0.57 0.71 0.85 W System clock: 49.152 MHz crystal; two DPLLs active; two 19.44 MHz input references in differential mode; two HSTL drivers at 644.53125 MHz; two 3.3 V CMOS drivers at 161.1328125 MHz and 80 pF capacitive load on CMOS output All Blocks Running 0.71 0.89 1.1 W System clock: 49.152 MHz crystal; two DPLLs active, all input references in differential mode; two HSTL drivers at 750 MHz; four 3.3 V CMOS drivers at 250 MHz and 80 pF capacitive load on CMOS outputs Full Power-Down 75 110 mW Typical configuration with no external pull-up or pull- down resistors; about 2/3 of this power is on VDD3 Incremental Power Dissipation Typical configuration; table values show the change in power due to the indicated operation Complete DPLL/APLL On/Off 171 214 257 mW This power delta is computed relative to the typical configuration; the blocks powered down include one reference input, one DPLL, one APLL, one P divider, two channel dividers, one HSTL driver, and one CMOS driver; roughly 2/3 of the power savings is on the 1.8 V supply Input Reference On/Off Differential Without Divide-by-2 19 25 31 mW Additional current draw is in the VDD3 domain only Differential With Divide-by-2 25 32 39 mW Additional current draw is in the VDD3 domain only Single-Ended (Without Divide-by-2) 5 6.6 8 mW Additional current draw is in the VDD3 domain only Output Distribution Driver On/Off LVDS (at 750 MHz) 12 17 22 mW Additional current draw is in the VDD domain only HSTL (at 750 MHz) 14 21 28 mW Additional current draw is in the VDD domain only 1.8 V CMOS (at 250 MHz) 14 21 28 mW A single 1.8 V CMOS output with an 80 pF load 3.3 V CMOS (at 250 MHz) 18 27 36 mW A single 3.3 V CMOS output with an 80 pF load SYSTEM CLOCK INPUTS (XOA, XOB) Table 4. Parameter Min Typ Max Unit Test Conditions/Comments SYSTEM CLOCK MULTIPLIER PLL Output Frequency Range 750 805 MHz VCO range may place limitations on nonstandard system clock input frequencies Phase Frequency Detector (PFD) Rate 150 MHz Frequency Multiplication Range 4 255 Assumes valid system clock and PFD rates SYSTEM CLOCK REFERENCE INPUT PATH Input Frequency Range 10 400 MHz Minimum Input Slew Rate 50 V/μs Minimum limit imposed for jitter performance; jitter performance affected if sine wave input ≤ 20 MHz Common-Mode Voltage 1.05 1.16 1.27 V Internally generated Differential Input Voltage Sensitivity 250 mV p-p Minimum voltage across pins required to ensure switching between logic states; the instantaneous voltage on either pin must not exceed supply rails; single-ended input can be accommodated by ac grounding complementary input; 1 V p-p recommended for optimal jitter performance System Clock Input Doubler Duty Cycle Amount of duty cycle variation that can be tolerated on the system clock input to use the doubler System Clock input = 50 MHz 45 50 55 % System Clock input = 20 MHz 46 50 54 % System Clock input = 16 MHz to 20 MHz 47 50 53 % Input Capacitance 3 pF Single-ended, each pin Input Resistance 4.1 kΩ |
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