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CDC2509BPWR Datasheet(PDF) 7 Page - Texas Instruments

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No. de pieza CDC2509BPWR
Descripción Electrónicos  3.3-V PHASE-LOCK LOOP CLOCK DRIVER
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Fabricante Electrónico  TI1 [Texas Instruments]
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CDC2509BPWR Datasheet(HTML) 7 Page - Texas Instruments

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CDC2509B
3.3V PHASELOCK LOOP CLOCK DRIVER
SCAS613C − SEPTEMBER 1998 − REVISED DECEMBER 2004
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
PHASE ADJUSTMENT SLOPE AND PHASE ERROR
vs
LUMPED FEEDBACK CAPACITANCE AT FBIN
0
5
10
15
20
25
30
35
40
45
50
VCC = 3.3 V
fc = 100 MHz
CLY = 30 pF
TA = 25°C
Phase Error Measured
from CLK to Y
CLF − Lumped Feedback Capacitance at FBIN − pF
20
0
−10
−20
−30
10
40
50
−40
−50
30
100
0
−50
−100
−150
50
200
250
−200
−250
150
Phase Error
Phase Adjustment Slope
Figure 3
PHASE ERROR
vs
CLOCK FREQUENCY
300
200
100
−100
35
45
55
65
75
85
95
105
115
125
0
400
VCC = 3.3 V
CLY = CLF = 30 pF
TA = 25°C
Phase Error Measured
from CLK to FBIN
fc − Clock Frequency − MHz
Figure 4
NOTES: A. CLY = Lumped capacitive load at Y
B. CLF = Lumped feedback capacitance at FBIN


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