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SN74F112NSR Datasheet(PDF) 4 Page - Texas Instruments |
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SN74F112NSR Datasheet(HTML) 4 Page - Texas Instruments |
4 / 13 page SN74F112 DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET SDFS048A – D2932, MARCH 1987 – REVISED OCTOBER 1993 2–4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 switching characteristics (see Note 3) PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 5 V, CL = 50 pF, RL = 500 Ω, TA = 25°C VCC = 4.5 V to 5.5 V, CL = 50 pF, RL = 500 Ω, TA = MIN to MAX† UNIT MIN TYP MAX MIN MAX fmax 110 130 100 MHz tPLH CLK QorQ 1.2 4.6 6.5 1.2 7.5 ns tPHL CLK Q or Q 1.2 4.6 6.5 1.2 7.5 ns tPLH PRE or CLR QorQ 1.2 4.1 6.5 1.2 7.5 ns tPHL PRE or CLR Q or Q 1.2 4.1 6.5 1.2 7.5 ns † For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. NOTE 3: Load circuits and waveforms are shown in Section 1. |
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