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CAT24C21ZD4E Datasheet(PDF) 4 Page - ON Semiconductor

No. de pieza CAT24C21ZD4E
Descripción Electrónicos  1 kb Dual Mode Serial EEPROM for VESA Plug-and-Play
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Fabricante Electrónico  ONSEMI [ON Semiconductor]
Página de inicio  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

CAT24C21ZD4E Datasheet(HTML) 4 Page - ON Semiconductor

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CAT24C21
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4
Transmit−Only Mode: (DDC1)
Upon power−up, the CAT24C21 will output valid data
only after it has been initialized. During initialization, data
will not be available until after the first nine clocks are sent
to the device (Figure 3). The starting address for the
transmit−only mode can be determined during initialization.
If the SDA pin is high during the first eight clocks, the
starting address will be 7FH. If the SDA pin is low during the
first eight clocks, the starting address will be 00H. During
the ninth clock, SDA will be in the high impedance state.
Data is transmitted in 8 bit words with the most significant
bit first, followed by a 9th ‘don’t care’ bit which will be in
the high impedance state (Figure 4). The CAT24C21 will
continuously sequence through the entire memory array as
long as VCLK is present and no falling edges on SCL are
detected. When the maximum address (7FH) is reached,
addressing will wrap around to the zero location (00H) and
transmitting will continue. The bi−directional mode clock
(SCL) pin must be held high for the device to remain in the
transmit−only mode.
Figure 2. Mode Transition
SCL
Transmit−Only Mode
Bi−Directional Mode
TVHZ
SDA
VCLK
Figure 3. Device Initialization for Transmit−only Mode
SCL
SDA
VCLK
SDA at high impedance for 9 clock cycles
Bit8
TVPU
12
3
4
56
78
9
10
11
12
13
14
15
Bit7 Bit6 Bit5 Bit4
TVAA
Figure 4. Transmit−Only Mode
SCL
SCL must remain high for transmit−only mode
Don’t
Care
SDA
VCLK
TVHIGH
TVLOW
Bit7
Bit6
Bit5
Bit4
(MSB)
Bit8
(LSB)
Bit3
Bit2
Bit1
Bit8
Bit7


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