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CAT28C65BP12 Datasheet(PDF) 7 Page - ON Semiconductor |
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CAT28C65BP12 Datasheet(HTML) 7 Page - ON Semiconductor |
7 / 13 page CAT28C65B 7 Doc. No. MD-1009, Rev. H © 2009 SCILLC. All rights reserved. Characteristics subject to change without notice ADDRESS CE OE WE tRC DATA OUT DATA VALID DATA VALID tCE tOE tOH tAA tOHZ tHZ VIH HIGH-Z tLZ tOLZ DEVICE OPERATION Read Data stored in the CAT28C65B is transferred to the data bus when WE is held high, and both OE and CE are held low. The data bus is set to a high impedance state when either CE or OE goes high. This 2-line control architecture can be used to eliminate bus contention in a system environment. Byte Write A write cycle is executed when both CE and WEare low, and OE is high. Write cycles can be initiated using either WE or CE, with the address input being latched on the Figure 3. Read Cycle Figure 4. Byte Write Cycle [ WE WE WE WE WE Controlled] ADDRESS CE OE WE DATA OUT tAS DATA IN DATA VALID HIGH-Z tCS tAH tCH tWC tOEH tBLC tDH tDS tWP RDY/BUSY tOES tRB HIGH-Z HIGH-Z |
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