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CAT24C256ZE-GT3 Datasheet(PDF) 5 Page - ON Semiconductor |
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CAT24C256ZE-GT3 Datasheet(HTML) 5 Page - ON Semiconductor |
5 / 18 page CAT24C256 http://onsemi.com 5 Table 9. A.C. CHARACTERISTICS − New Product (Rev E) (Notes 14, 15) (VCC = 1.8 V to 5.5 V, TA = −40°C to +85°C and VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C, unless otherwise specified.) Symbol Parameter Standard VCC = 1.8 V − 5.5 V Fast VCC = 1.8 V − 5.5 V Fast−Plus VCC = 2.5 V − 5.5 V TA = −405C to +855C Units Min Max Min Max Min Max FSCL Clock Frequency 100 400 1,000 kHz tHD:STA START Condition Hold Time 4 0.6 0.25 ms tLOW Low Period of SCL Clock 4.7 1.3 0.45 ms tHIGH High Period of SCL Clock 4 0.6 0.40 ms tSU:STA START Condition Setup Time 4.7 0.6 0.25 ms tHD:DAT Data In Hold Time 0 0 0 ms tSU:DAT Data In Setup Time 250 100 50 ns tR (Note 16) SDA and SCL Rise Time 1,000 300 100 ns tF (Note 16) SDA and SCL Fall Time 300 300 100 ns tSU:STO STOP Condition Setup Time 4 0.6 0.25 ms tBUF Bus Free Time Between STOP and START 4.7 1.3 0.5 ms tAA SCL Low to Data Out Valid 3.5 0.9 0.40 ms tDH Data Out Hold Time 50 50 50 ns Ti (Note 16) Noise Pulse Filtered at SCL and SDA Inputs 50 50 50 ns tSU:WP WP Setup Time 0 0 0 ms tHD:WP WP Hold Time 2.5 2.5 1 ms tWR Write Cycle Time 5 5 5 ms tPU (Notes 16, 17) Power-up to Ready Mode 1 1 0.1 1 ms 14.Test conditions according to “A.C. Test Conditions” table. 15.The New product Rev E is identified by letter “E” or a dedicated marking code on top of the package. 16.Tested initially and after a design or process change that affects this parameter. 17.tPU is the delay between the time VCC is stable and the device is ready to accept commands. |
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