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CAT34C02HU3IGT Datasheet(PDF) 2 Page - ON Semiconductor |
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CAT34C02HU3IGT Datasheet(HTML) 2 Page - ON Semiconductor |
2 / 14 page CAT34C02 http://onsemi.com 2 Table 1. ABSOLUTE MAXIMUM RATINGS Parameter Rating Unit Operating Temperature −45 to +130 °C Storage Temperature −65 to +150 °C Voltage on Any Pin with Respect to Ground (Note 1) −0.5 to +6.5 V Voltage on Pin A0 with Respect to Ground −0.5 to +10.5 V Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. The DC input voltage on any pin should not be lower than −0.5 V or higher than VCC + 0.5 V. During transitions, the voltage on any pin may undershoot to no less than −1.5 V or overshoot to no more than VCC + 1.5 V, for periods of less than 20 ns. Table 2. RELIABILITY CHARACTERISTICS (Note 2) Symbol Parameter Min Units NEND (Note 3) Endurance 1,000,000 Program/ Erase Cycles TDR Data Retention 100 Years 2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100 and JEDEC test methods. 3. Page Mode, VCC = 5 V, 25°C Table 3. D.C. OPERATING CHARACTERISTICS (VCC = 1.7 V to 5.5 V, TA = −40°C to +85°C, unless otherwise specified.) Symbol Parameter Test Conditions Min Max Units ICC Supply Current VCC < 3.6 V, fSCL = 100 kHz 1 mA VCC > 3.6 V, fSCL = 400 kHz 2 ISB Standby Current All I/O Pins at GND or VCC TA = −40°C to +85°C VCC ≤ 3.3 V 1 mA TA = −40°C to +85°C VCC > 3.3 V 3 IL I/O Pin Leakage Pin at GND or VCC 2 mA VIL Input Low Voltage −0.5 0.3 x VCC V VIH Input High Voltage 0.7 x VCC VCC + 0.5 VOL Output Low Voltage VCC > 2.5 V, IOL = 3 mA 0.4 VCC < 2.5 V, IOL = 1 mA 0.2 Table 4. PIN IMPEDANCE CHARACTERISTICS (VCC = 1.7 V to 5.5 V, TA = −40°C to +85°C, unless otherwise specified.) Symbol Parameter Conditions Max Units CIN (Note 4) SDA I/O Pin Capacitance VIN = 0 V, f = 1.0 MHz, VCC = 5.0 V 8 pF Other Input Pins 6 IWP (Note 5) WP Input Current VIN < VIH, VCC = 5.5 V 130 mA VIN < VIH, VCC = 3.6 V 120 VIN < VIH, VCC = 1.7 V 80 VIN > VIH 2 IA (Note 5) Address Input Current (A0, A1, A2) Product Rev H VIN < VIH, VCC = 5.5 V 50 mA VIN < VIH, VCC = 3.6 V 35 VIN < VIH, VCC = 1.7 V 25 VIN > VIH 2 4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100 and JEDEC test methods. 5. When not driven, the WP, A0, A1 and A2 pins are pulled down to GND internally. For improved noise immunity, the internal pull-down is relatively strong; therefore the external driver must be able to supply the pull-down current when attempting to drive the input HIGH. To conserve power, as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x VCC), the strong pull-down reverts to a weak current source. |
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