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AD1858JRSRL Datasheet(PDF) 5 Page - Analog Devices |
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AD1858JRSRL Datasheet(HTML) 5 Page - Analog Devices |
5 / 16 page AD1857/AD1858 REV. 0 –5– PIN LIST Digital Audio Serial Input Interfaces Pin Name Number I/O Description SDATA 20 I Serial input, MSB first, containing two channels of 16, 18 or 20 bits (AD1857) or 16 bits (AD1858) of twos complement data per channel. BCLK 19 I Bit clock input for input data. Need not run continuously; may be gated or used in a burst fashion. L RCLK 18 I Left/ right clock input for input data. Must run continuously. MODE 3 I Input serial data port mode control. Selects between I 2S-justified (HI) and left-justified (LO) on the AD1857. Selects between DSP serial port style mode (HI) and right- justified (LO) on the AD1858. The state of the mode pin should be changed only when the AD1857/AD1858 is held in reset ( PD/RST LO). Otherwise, the AD1857/ AD1858 serial port may lose synchronism. Control and Clock Signals Pin Name Number I/O Description PD/RST 2 I Power-Down/Reset. The AD1857/AD1858 are placed in a low power consumption “sleep” mode when this pin is held LO. The AD1857/AD1858 are reset on the rising edge of this signal. Connect HI for normal operation. DEEMP 5 I De-emphasis. Digital de-emphasis is enabled when this input signal is HI. This is used to impose a 50/15 µs response characteristic on the output audio spectrum at an assumed 44.1 kHz sample rate. MUTE 15 I Mute. Assert HI to mute both stereo analog outputs of the AD1857/AD1858. Deassert LO for normal operation. MCLK 1 I Master Clock Input. Connect to an external clock source at either 256 or 384 times the intended sample frequency as determined by the 384/ 256 pin. Must be synchro- nous with L RCLK, but may have any phase with respect to LRCLK. 384/ 256 6 I Selects the master clock mode as either 384 times the intended sample frequency (HI) or 256 times the intended sample frequency (LO). The state of this input should be hardwired to logic LO or logic HI or may be changed while the AD1857/ AD1858 is in power-down/reset. It must not be changed while the AD1857/AD1858 is operational. Analog Signals Pin Name Number I/O Description FILT 11 O Voltage Reference Filter Capacitor Connection. Bypass and decouple the voltage reference with parallel 10 µF and 0.1 µF capacitors to the AGND pin. CMOUT 10 O Voltage Reference Common Mode Output. Should be decoupled with 10 µF capacitor to the AGND pin or plane. This output is available externally for dc coupling and level-shifting. CMOUT should not have any signal dependent load, or used where it will sink or source current. OUTL 8 O Left channel line level analog output. OUTR 13 O Right channel line level analog output. Power Supply Connections and Miscellaneous Pin Name Number I/O Description AVDD 7, 14 I Analog Power Supply. Connect to analog +5 V supply. AGND 9, 12 I Analog Ground. DVDD 17 I Digital Power Supply. Connect to digital +5 V supply. DGND 16 I Digital Ground. N/C 4 No Connect. Reserved. Do not connect. |
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