PD104SLG

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7-4) Input / Output signal timing chart

(A) Vertical Timing

X,1

X,2

X,3 X,4

X,598 X,599 X,600

X,Y

CLK

ENAB

R5~R0

G5~G0

B5~B0

(B) Horizontal Timing

CLK

ENAB

R5~R0

G5~G0

B5~B0

1,Y 2,Y 3,Y 4,Y 5,Y 6,Y 7,Y

X,Y

798,Y 800,Y

797,Y 799,Y

P-511-525(V:3)