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SN74LS190D Datasheet(PDF) 6 Page - Motorola, Inc |
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SN74LS190D Datasheet(HTML) 6 Page - Motorola, Inc |
6 / 10 page 5-346 FAST AND LS TTL DATA SN54/74LS190 • SN54/74LS191 AC CHARACTERISTICS (TA = 25°C) Symbol Parameter Limits Unit Test Conditions Symbol Parameter Min Typ Max Unit Test Conditions fMAX Maximum Clock Frequency 20 25 MHz VCC = 5.0 V CL = 15 pF tPLH tPHL Propagation Delay, PL to Output Q 22 33 33 50 ns VCC = 5.0 V CL = 15 pF tPLH tPHL Data to Output Q 20 27 32 40 ns VCC = 5.0 V CL = 15 pF tPLH tPHL Clock to RC 13 16 20 24 ns VCC = 5.0 V CL = 15 pF tPLH tPHL Clock to Output Q 16 24 24 36 ns VCC = 5.0 V CL = 15 pF tPLH tPHL Clock to TC 28 37 42 52 ns CL = 15 pF tPLH tPHL U / D to RC 30 30 45 45 ns tPLH tPHL U / D to TC 21 22 33 33 ns tPLH tPHL CE to RC 21 22 33 33 ns AC SETUP REQUIREMENTS (TA = 25°C) Symbol Parameter Limits Unit Test Conditions Symbol Parameter Min Typ Max Unit Test Conditions tW CP Pulse Width 25 ns VCC = 5.0 V tW PL Pulse Width 35 ns VCC = 5.0 V ts Data Setup Time 20 ns VCC = 5.0 V th Data Hold Time 5.0 ns CC = 5.0 V trec Recovery Time 40 ns DEFINITIONS OF TERMS SETUP TIME (ts) is defined as the minimum time required for the correct logic level to be present at the logic input prior to the clock transition from LOW-to-HIGH in order to be recognized and transferred to the outputs. HOLD TIME (th) is defined as the minimum time following the clock transition from LOW-to-HIGH that the logic level must be maintained at the input in order to ensure continued recogni- tion. A negative HOLD TIME indicates that the correct logic level may be released prior to the clock transition from LOW- to-HIGH and still be recognized. RECOVERY TIME (trec) is defined as the minimum time required between the end of the reset pulse and the clock transition from LOW-to-HIGH in order to recognize and transfer HIGH data to the Q outputs. |
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