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CAT33C804APATE13 Datasheet(PDF) 7 Page - Catalyst Semiconductor |
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CAT33C804APATE13 Datasheet(HTML) 7 Page - Catalyst Semiconductor |
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7 / 14 page  Preliminary CAT33C804A 7 Doc. No. 25044-00 2/98 also go to the high impedance state if an error condition is detected. In the event an ENABLE BUSY instruction has not been sent, a READ STATUS register instruction can be executed. This also tells the user whether the part is in a program/erase cycle or an error condtion. When the device is in a program/erase cycle it will output an 8 bit status word. If it does not, it is in an error condition. PE The Parity Enable pin is a TTL compatible input. If the PE pin is set HIGH, the device will be configured to commu- nicate using even parity, and if the pin is set LOW, it will use no parity. In this case, instructions or data that include parity bits will not be interpreted correctly. Note: The PE input is internally pulled down to GND (i.e. default = no parity). As with all CMOS devices, CS, CLK and DI inputs must be connected to either HIGH or LOW, and not left floating. ERR The Error indication pin is an open drain output. If either an instruction or parity error exists, the ERR pin will output a “0” until the device is reset. This can be done by pulsing CS LOW. Figure 6. Read Timing (x8 Format) CS DI HIGH-Z DO OP0–OP7 OP CODE A8–A15 ADDRESS A0–A7 ADDRESS D0–D7 DATA CLK VCC 33C804 F09 Figure 7. Read Timing (x16 Format) CS DI HIGH-Z DO OP0–OP7 OP CODE A0–A7 ADDRESS D8–D15 DATA CLK VCC D0–D7 DATA HIGH-Z 33C804 F10 |
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