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2

Unit Loading/Fan Out

Functional Description

The 74F373 contains eight D-type latches with 3-STATE

output buffers. When the Latch Enable (LE) input is HIGH,

the latches are transparent, i.e., a latch output will change

state each time its D input changes. When LE is LOW, the

latches store the information that was present on the D

inputs a setup time preceding the HIGH-to-LOW transition

of LE. The 3-STATE buffers are controlled by the Output

Enable (OE) input. When OE is LOW, the buffers are in the

bi-state mode. When OE is HIGH the buffers are in the high

impedance mode but this does not interfere with entering

new data into the latches.

Truth Table

H

= HIGH Voltage Level

L

= LOW Voltage Level

X

= Immaterial

Z

= High Impedance State

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

Pin Names

Description

U.L.

HIGH/LOW

Data Inputs

1.0/1.0

20

µA/−0.6 mA

LE

Latch Enable Input (Active HIGH)

1.0/1.0

20

µA/−0.6 mA

OE

Output Enable Input (Active LOW)

1.0/1.0

20

µA/−0.6 mA

3-STATE Latch Outputs

150/40 (33.3)

−3 mA/24 mA (20 mA)

Inputs

Output

LE

OE

HL

H

H

HL

L

L

LL

X

XHX

Z