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BD37033FVME2 Datasheet(PDF) 9 Page - Rohm |
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BD37033FVME2 Datasheet(HTML) 9 Page - Rohm |
9 / 41 page 9/38 Datasheet BD37033FV-M TSZ02201-0C2C0E100000-1-2 © 2013 ROHM Co., Ltd. All rights reserved. 3.NOV.2013 Rev.002 www.rohm.com TSZ22111 ・15・001 I 2C BUS CONTROL SIGNAL SPECIFICATION (1) Electrical specifications and timing for bus lines and I/O stages Figure 16. Definition of timing on the I 2C-bus Table 1 Characteristics of the SDA and SCL bus lines for I 2C-bus devices(Ta=25 ℃ , VCC=8.5V) Parameter Symbol Fast-mode I 2C-bus Unit Min. Max. 1 SCL clock frequency fSCL 0 400 kHz 2 Bus free time between a STOP and START condition tBUF 1.3 - µS 3 Hold time (repeated) START condition. After this period, the first clock pulse is generated tHD;STA 0.6 - µS 4 LOW period of the SCL clock tLOW 1.3 - µS 5 HIGH period of the SCL clock tHIGH 0.6 - µS 6 Set-up time for a repeated START condition tSU;STA 0.6 - µS 7 Data hold time tHD;DAT 0 - µS 8 Data set-up time tSU;DAT 100 - ns 9 Set-up time for STOP condition tSU;STO 0.6 - µS All values referred to VIH min. and VIL max. Levels (see Table 2). Table 2 Characteristics of the SDA and SCL I/O stages for I 2C-bus devices Parameter Symbol Fast-mode devices Unit Min. Max. 10 LOW level input voltage VIL -0.3 1 V 11 HIGH level input voltage VIH 2.3 5 V 12 Pulse width of spikes which must be suppressed by the input filter. tSP 0 50 ns 13 LOW level output voltage: at 3mA sink current VOL1 0 0.4 V 14 Input current each I/O pin with an input voltage between 0.4V and 4.5V Ii -10 10 µA SDA S S CL t LOW t R t HD;DAT P t HD;ST A t HIG H t BUF t F t SU;DAT t S U; STA t S U; STO t SP t HD;STA Sr P Figure 17. Command timing example in the I2C data transmission |
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