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74HCT4053D-Q100 Datasheet(PDF) 3 Page - NXP Semiconductors |
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74HCT4053D-Q100 Datasheet(HTML) 3 Page - NXP Semiconductors |
3 / 30 page 74HC_HCT4053_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 2 — 22 November 2012 3 of 30 NXP Semiconductors 74HC4053-Q100; 74HCT4053-Q100 Triple 2-channel analog multiplexer/demultiplexer 5. Functional diagram Fig 1. Functional diagram 001aak341 LOGIC LEVEL CONVERSION 11 16 VCC 13 1Y1 S1 LOGIC LEVEL CONVERSION DECODER LOGIC LEVEL CONVERSION 12 1Y0 14 1Z 1 2Y1 2 2Y0 15 2Z 3 3Y1 5 3Y0 43Z 10 S2 9 87 VEE GND S3 6 E Fig 2. Logic symbol Fig 3. IEC logic symbol 001aae125 1Y0 12 1Y1 S1 13 11 S2 10 S3 9 6 E 2Y0 2 2Y1 1 3Y0 5 3Y1 3 3Z 4 2Z 15 1Z 14 001aae126 6 EN 11 # # # MUX/DMUX 12 13 × 0 1 0/1 0 1 14 10 2 1 15 9 5 3 4 |
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