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E-L6205PD Datasheet(PDF) 9 Page - STMicroelectronics

No. de pieza E-L6205PD
Descripción Electrónicos  DMOS DUAL FULL BRIDGE DRIVER
Download  21 Pages
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Fabricante Electrónico  STMICROELECTRONICS [STMicroelectronics]
Página de inicio  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

E-L6205PD Datasheet(HTML) 9 Page - STMicroelectronics

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L6205
NON-DISSIPATIVE OVERCURRENT PROTECTION
The L6205 integrates an Overcurrent Detection Circuit (OCD). This circuit provides protection against a short
circuit to ground or between two phases of the bridge. With this internal over current detection, the external cur-
rent sense resistor normally used and its associated power dissipation are eliminated. Figure 7 shows a simpli-
fied schematic of the overcurrent detection circuit.
To implement the over current detection, a sensing element that delivers a small but precise fraction of the out-
put current is implemented with each high side power MOS. Since this current is a small fraction of the output
current there is very little additional power dissipation. This current is compared with an internal reference cur-
rent IREF. When the output current in one bridge reaches the detection threshold (typically 5.6A) the relative
OCD comparator signals a fault condition. When a fault condition is detected, the EN pin is pulled below the turn
off threshold (1.3V typical) by an internal open drain MOS with a pull down capability of 4mA. By using an ex-
ternal R-C on the EN pin, the off time before recovering normal operation can be easily programmed by means
of the accurate thresholds of the logic inputs.
Figure 7. Overcurrent Protection Simplified Schematic
Figure 8 shows the Overcurrent Detection operation. The Disable Time tDISABLE before recovering normal opera-
tion can be easily programmed by means of the accurate thresholds of the logic inputs. It is affected whether by
CEN and REN values and its magnitude is reported in Figure 9. The Delay Time tDELAY before turning off the bridge
when an overcurrent has been detected depends only by CEN value. Its magnitude is reported in Figure 10.
CEN is also used for providing immunity to pin EN against fast transient noises. Therefore the value of CEN
should be chosen as big as possible according to the maximum tolerable Delay Time and the REN value should
be chosen according to the desired Disable Time.
The resistor REN should be chosen in the range from 2.2KΩ to 180KΩ. Recommended values for REN and CEN
are respectively 100K
Ω and 5.6nF that allow obtaining 200µs Disable Time.
+
OVER TEMPERATURE
IREF
(I1A+I2A) / n
I1A / n
POWER SENSE
1 cell
POWER SENSE
1 cell
POWER DMOS
n cells
POWER DMOS
n cells
HIGH SIDE DMOSs OF
THE BRIDGE A
OUT1A
OUT2A
VSA
I1A
I2A
I2A / n
OCD
COMPARATOR
TO GATE
LOGIC
INTERNAL
OPEN-DRAIN
RDS(ON)
40
Ω TYP.
CEN
REN
ENA
+5V
µC or LOGIC
D02IN1353


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