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CAT24WC16W-TE13D Datasheet(PDF) 6 Page - Catalyst Semiconductor |
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CAT24WC16W-TE13D Datasheet(HTML) 6 Page - Catalyst Semiconductor |
6 / 9 page CAT24WC01/02/04/08/16 6 Doc. No. 25051-00 3/98 S-1 line) when its address matches the transmitted slave address. The CAT24WC01/02/04/08/16 then performs a Read or Write operation depending on the state of the R/ W bit. Acknowledge After a successful data transfer, each receiving device is required to generate an acknowledge. The Acknowledg- ing device pulls down the SDA line during the ninth clock cycle, signaling that it received the 8 bits of data. The CAT24WC01/02/04/08/16 responds with an ac- knowledge after receiving a START condition and its slave address. If the device has been selected along with a write operation, it responds with an acknowledge after receiving each 8-bit byte. When the CAT24WC01/02/04/08/16 is in a READ mode it transmits 8 bits of data, releases the SDA line, and monitors the line for an acknowledge. Once it receives this acknowledge, the CAT24WC01/02/04/08/16 will continue to transmit data. If no acknowledge is sent by the Master, the device terminates data transmission and waits for a STOP condition. WRITE OPERATIONS Byte Write In the Byte Write mode, the Master device sends the START condition and the slave address information (with the R/ W bit set to zero) to the Slave device. After the Slave generates an acknowledge, the Master sends the byte address that is to be written into the address pointer of the CAT24WC01/02/04/08/16. After receiving another acknowledge from the Slave, the Master device transmits the data byte to be written into the addressed memory location. The CAT24WC01/02/04/08/16 ac- knowledge once more and the Master generates the STOP condition, at which time the device begins its internal programming cycle to nonvolatile memory. While this internal cycle is in progress, the device will not respond to any request from the Master device. Page Write The CAT24WC01/02/04/08/16 writes up to 16 bytes of data in a single write cycle, using the Page Write operation. The Page Write operation is initiated in the same manner as counter will ‘wrap around’ to address Figure 5. Slave Address Bits 1 0 1 0 A2 A1 A0 R/W 1 0 1 0 A2 A1 a8 R/W 1 0 1 0 A2 a9 a8 R/W 1 0 1 0 a10 a9 a8 R/W 24WC01/02 24WC04 24WC08 24WC16 * A0, A1 and A2 correspond to pin 1, pin 2 and pin 3 of the device. ** a8, a9 and a10 correspond to the address of the memory array address word. *** A0, A1 and A2 must compare to its corresponding hard wired input pins (pins 1, 2 and 3). |
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