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CS5132GDW24 Datasheet(PDF) 9 Page - Cherry Semiconductor Corporation |
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CS5132GDW24 Datasheet(HTML) 9 Page - Cherry Semiconductor Corporation |
9 / 19 page Figure 4: Pulse-by-Pulse Regulation during Soft Start (2µs/div). Channel 1 - Regulator Output Voltage (0.2V/div) Channel 2 Ð Inductor Switching Node (5V/div) Channel 3 - VCC (10V/div) Channel 4 - Regulator Input Voltage (5V/div) Figure 5: Start-up with COMP pre-charged to 2V (2ms/div). Channel 1 - Regulator Output Voltage (1V/div) Channel 2 - COMP Pin (1V/div) Channel 3 - VCC (10V/div) Channel 4 - Regulator Input Voltage (5V/div) When driving large capacitive loads, the COMP must charge slowly enough to avoid tripping the CS5132 over- current protection. The following equation can be used to ensure unconditional start-up. < where ICHG = COMP Source Current (30µA typical); CCOMP = COMP Capacitor value (0.1µF typical); ILIM = Current Limit Threshold; ILOAD = Load Current during start-up; COUT = Total Output Capacitance. Normal Operation During Normal operation, Switch Off-Time is constant and set by the COFF capacitor. Switch On-Time is adjusted by the V2 TM Control loop to maintain regulation. This results in changes in regulator switching frequency, duty cycle, and output ripple in response to changes in load and line. Output voltage ripple will be determined by inductor rip- ple current and the ESR of the output capacitors Transient Response The CS5132 V2 TM Control LoopÕs 200ns reaction time pro- vides unprecedented transient response to changes in input voltage or output current. Pulse-by-pulse adjustment of duty cycle is provided to quickly ramp the inductor current to the required level. Since the inductor current cannot be changed instantaneously, regulation is maintained by the output capacitor(s) during the time required to slew the inductor current. Overall load transient response is further improved through a feature called ÒAdaptive Voltage PositioningÓ. This tech- nique pre-positions the output voltage to reduce total out- put voltage excursions during changes in load. Holding tolerance to 1% allows the error amplifiers refer- ence voltage to be targeted +25mV high without compro- mising DC accuracy. A ÒDroop ResistorÓ, implemented through a PC board trace, connects the Error Amps feed- back pin (VFB) to the output capacitors and load and carries the output current. With no load, there is no DC drop across this resistor, producing an output voltage tracking the Error amps, including the +25mV offset. When the full load current is delivered, a 50mV drop is developed across this resistor. This results in output voltage being offset - 25mV low. The result of Adaptive Voltage Positioning is that addition- al margin is provided for a load transient before reaching the output voltage specification limits. When load current suddenly increases from its minimum level, the output is pre-positioned +25mV. Conversely, when load current sud- denly decreases from its maximum level, the output is pre- positioned -25mV. For best Transient Response, a combina- tion of a number of high frequency and bulk output capaci- tors are usually used. Slope Compensation The V2 TM control method uses a ramp signal, generated by the ESR of the output capacitors, that is proportional to the ripple current through the inductor. To maintain regula- tion, the V2 TM control loop monitors this ramp signal, through the PWM comparator, and terminates the switch on-time. The stringent load transient requirements of modern micro- processors require the output capacitors to have very low ESR. The resulting shallow slope presented to the PWM comparator, due to the very low ESR, can lead to pulse width jitter and variation caused by both random or syn- chronous noise. ILIM Ð ILOAD COUT ICHG CCOMP Soft Start @ COMP > 1.06V OCP @ VCC > 8.5V Duty Cycle = VOUT / VIN 0.27V / 3.54V = 7% » 5.2% Application Information: continued 9 |
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