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CS22230 Datasheet(PDF) 6 Page - Cirrus Logic

No. de pieza CS22230
Descripción Electrónicos  WIRELESS PCI/USB CONTROLLER
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Fabricante Electrónico  CIRRUS [Cirrus Logic]
Página de inicio  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS22230 Datasheet(HTML) 6 Page - Cirrus Logic

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CS22230 Mini PCI / USB Wireless Controller
6 of 29
DS558PP1
Rev. 1.0
www.cirrus.com
3.2
Digital Wireless Radio Interface
The CS22230 digital radio MAC I/F supports multiple radio baseband and RF interfaces. The
baseband registers can be programmed during the configuration time using the control port
interface. The MAC also provides the capability of programming the signal, service and
length on per packet basis without ARM intervention. This significantly improves the
performance of the system.
There are three primary digital interface ports for the CS22230 that are used for configuration
and during normal operation.
These ports are:
The Control Port, which is used to configure, set power consumption modes, write and/or
read the status of the radio base band registers.
The TX Port, which is used to output the data that needs to be transmitted from the
network processor.
The RX Port, which is used to input the received demodulated data to the network
processor.
3.3
FEC Codec
The FEC codec performs Reed-Solomon code encoding to protect the data before it is
transmitted to a noisy channel. It is a similar code as employed by digital broadcast industry,
such as ITU-T J.83 for DVB. The RS(255, 239) code implemented by the SWG2710 can
reduce error probability to 1/10e-9 in a typical 1/10e-3 error rate environment.
The
encoder/decoder can be programmed to vary the coding block length (N) and correctable
error (t) to optimize the tradeoff between channel utilization and data protection. The range of
N is currently setto befrom 50to255,and the t is 8. The symbol size is fixed at 8 bits.
Coding parameters can be set real time, allowing maximum flexibility for the system to adjust
the FEC setting, such as block size, in order to optimize channel efficiency. The encoder also
has a very low latency of two cycles. Both the encoder and decoder are fully pipelined in
structure to achieve single cycle throughput. The FEC can be disabled in firmware.


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