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CS22230 Datasheet(PDF) 10 Page - Cirrus Logic |
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CS22230 Datasheet(HTML) 10 Page - Cirrus Logic |
10 / 29 page CS22230 Mini PCI / USB Wireless Controller 10 of 29 DS558PP1 Rev. 1.0 www.cirrus.com SMA0 Output Address bit0. The address bus specifies either the row address or column address. Also shared as boot-rom address bit0. This pin should be pull- down. SMA1 Output Address bit1. Also shared as boot-rom address bit1. Also used during reset to latch in the strap value for Mini PCI sel; if set to a '1' implies Mini PCI mode. SMA2 Output Address bit2. Also shared as boot-rom address bit2. Also used during reset to latch in the strap value for usbsel; if set to a '1' implies usb mode. SMA3 Output Address bit3. Also shared as boot-rom address bit3. This pin should be pull-down. SMA4 Output Address bit4. Also shared as boot-rom address bit4. Also used during reset to latch in the strap value for romcfg; if set to a '1' implies Mini PCI configuration data should be downloaded from ROM. SMA5 Output Address bit5. Also shared as boot-rom address bit5. Also used during reset to latch in the strap value for test_rst_enb; if set to a '0' implies normal operation mode. SMA6 Output Address bit6. Also shared as boot-rom address bit6. Also used during reset to latch in the strap value for freq_sel(0). Freq_sel(2:0) is used to select the multiplication factor for the internal PLL (000=1x, and 111=8x). SMA7 Output Address bit7. Also shared as boot-rom address bit7. Also used during reset to latch in the strap value for freq_sel(1). Freq_sel(2:0) is used to select the multiplication factor for the internal PLL (000=1x, and 111=8x). SMA8 Output Address bit8. Also shared as boot-rom address bit8. Also used during reset to latch in the strap value for freq_sel(2). Freq_sel(2:0) is used to select the multiplication factor for the internal PLL (000=1x, and 111=8x). SMA9 Output Address bit9. Also shared as boot-rom address bit9. Also used during reset to latch in the strap value for sdram_delay(0). Sdram_delay(2:0) is used to select the delay factor for the internal memory clock (000=0ns, and 111=1.75ns with each .25ns increments). |
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