CS5360-KS datasheet(6/22 Pages) CIRRUS

No. de pieza	CS5360-KS

Descripción Electrónicos	24-Bit Stereo A/D Converter for Digital Audio

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Fabricante Electrónico	CIRRUS [Cirrus Logic]

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CS5360

6

DS280PP2

SWITCHING CHARACTERISTICS (T

A = 25 °C; VA+ = 5 V ±5%; Inputs: Logic 0 = 0 V,

Logic 1 = VA+ = VD+; CL = 20 pF)

Notes: 7. SCLK Rising for Mode 1

8.

9.

10. Pulse Width High for Mode 1

11. Pulse Width Low for Mode 1

12.

13.

14. SCLK Falling for Mode 1

15.

Parameter

Symbol

Min

Typ

Max

Unit

Output Sample Rate

FS

8.0

-

50

kHz

MCLK Period

MCLK / LRCK = 256

MCLK / LRCK = 384

MCLK / LRCK = 512

tclkw

78

52

39

-

1953

1302

976

ns

MCLK Low

MCLK / LRCK = 256

MCLK / LRCK = 384

MCLK / LRCK = 512

tclkl

31

20

15

-

ns

MCLK High

MCLK / LRCK = 256

MCLK / LRCK = 384

MCLK / LRCK = 512

tclkh

31

20

15

-

ns

Peak Update Pulse Width

pupulse

20

-

ns

Master Mode

SCLK Falling to LRCK

(Note 7)

tmslr

-10

-

10

ns

SCLK Falling to SDATA Valid

(Note 7)

tsdo

-10

-

35

ns

SCLK Duty Cycle

-

50

-

%

SCLK Falling to Frame Valid

(Note 7)

tsfo

-10

-

Note 8

ns

LRCK Edge to OVFL Valid

tovfl

-10

-

30

ns

LRCK Edge to OVFL Edge Delay

tovfl

-10

-

Note 12

ns

Slave Mode

LRCK Duty Cycle

25

50

75

%

SCLK Period

tsclkw

Note 9

-

ns

SCLK Pulse Width Low

(Note 10)

tsclkl

Note 13

-

ns

SCLK Pulse Width High

(Note 11)

tsclkh

50

-

ns

SCLK Falling to SDATA Valid

(Note 7)

tdss

-

Note 13

ns

LRCK Edge to MSB Valid

tlrdss

-

Note 13

ns

SCLK Rising to LRCK Edge Delay

(Note 14)

tslr1

50

-

ns

LRCK Edge to Rising SCLK Setup Time

(Note 14)

tslr2

Note 13

-

ns

SCLK Falling to Frame Delay

tsfo

-

Note 15

ns

1

1024

() F

S

()

-------------------------------

30 ns

+

1

96

() F

S

()

------------------------

1

512

() F

S

()

----------------------------20 ns

+

1

512

() F

S

()

----------------------------50 ns

+

1

384

() F

S

()

----------------------------35 ns

+

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