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M-8888-01P Datasheet(PDF) 7 Page - Clare, Inc. |
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M-8888-01P Datasheet(HTML) 7 Page - Clare, Inc. |
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7 / 14 page  Staus Register Description Bit Name Status Flag Set Status Flag Cleared b0 IRQ Interrupt has occurred. Bit one (b1) Interrupt is inactive. Cleared after and/or bit 2 (b2) is set.status register is read. b1 Transmit data register empty Pause duration has terminated and transmitter Cleared after status register is read or (burst mode only) is ready for new data. when not in burst mode. b2 Receive data register full. Valid data is in the receive data register. Cleared after status register is read. b3 Delayed Steering Set on valid detection of the absence of a Cleared on detection of a valid DTMF DTMF signal. signal. b3 b2 b1 b0 RSEL IRQ CP/DTMF TOUT M-8888 www.clare.com 7 Rev. 1 Common Crystal Connection RS0 RD WR Function 0 1 0 Write to transmitter 0 0 1 Read from receiver 1 1 0 Write to control register 1 0 1 Read from status register Internal Register Functions CRA Bit Positions b3 b2 b1 b0 C/R S/D TEST BURST CRB Bit Positions Equations Application Circuit (Single-Ended Input) |
Número de pieza similar - M-8888-01P |
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Descripción similar - M-8888-01P |
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