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DAC34H84 Datasheet(PDF) 8 Page - Texas Instruments

No. de pieza DAC34H84
Descripción Electrónicos  Quad-Channel, 16-Bit, 1.25 GSPS Digital-to-Analog Converter (DAC)
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Fabricante Electrónico  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
Logo TI1 - Texas Instruments

DAC34H84 Datasheet(HTML) 8 Page - Texas Instruments

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DAC34H84
SLAS751B
– MARCH 2011 – REVISED SEPTEMBER 2011
www.ti.com
ELECTRICAL CHARACTERISTICS
– DC SPECIFICATIONS
(1)
over recommended operating free-air temperature range, nominal supplies, IOUTFS = 20mA (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Resolution
16
Bits
DC ACCURACY
DNL
Differential nonlinearity
±2
LSB
1 LSB = IOUTFS/2
16
INL
Integral nonlinearity
±4
LSB
ANALOG OUTPUT
Coarse gain linearity
±0.04
LSB
Offset error
Mid code offset
±0.001
%FSR
With external reference
±2
%FSR
Gain error
With internal reference
±2
%FSR
Gain mismatch
With internal reference
±2
%FSR
Full scale output current
10
20
30
mA
Output compliance range
–0.5
0.6
V
Output resistance
300
k
Ω
Output capacitance
5
pF
REFERENCE OUTPUT
VREF
Reference output voltage
1.2
V
Reference output current(2)
100
nA
REFERENCE INPUT
VEXTIO
Input voltage range
0.6
1.2
1.25
V
External Reference Mode
Input resistance
1
M
Ω
Small signal bandwidth
472
kHz
Input capacitance
100
pF
TEMPERATURE COEFFICIENTS
Offset drift
±1
ppm/
°C
with external reference
±15
ppm/
°C
Gain drift
with internal reference
±30
ppm/
°C
Reference voltage drift
±8
ppm/
°C
POWER SUPPLY(3)
AVDD, IOVDD, PLLAVDD
3.14
3.3
3.46
V
CLKVDD, DACVDD, DIGVDD
1.14
1.2
1.26
V
IOVDD2
1.71
3.3
3.45
V
PSRR
Power supply rejection ratio
DC tested
±0.25
%FSR/V
POWER CONSUMPTION
I(AVDD)
Analog supply current(4)
135
165
mA
MODE 1 (5)
I(DIGVDD)
Digital supply current
740
820
mA
fDAC = 1.25GSPS, 2x interpolation, Mixer on,
I(DACVDD)
DAC supply current
40
60
mA
QMC on, invsinc on, PLL enabled, 20mA FS
I(CLKVDD)
Clock supply current
100
120
mA
output, IF = 200MHz
P
Power dissipation
1500
1750
mW
(1)
Measured differentially across IOUTP/N with 25
Ω each to GND.
(2)
Use an external buffer amplifier with high impedance input to drive any external load.
(3)
To ensure power supply accuracy and to account for power supply filter network loss at operating conditions, the use of the ATEST
function in register config27 to check the internal power supply nodes is recommended.
(4)
Includes AVDD, PLLAVDD, and IOVDD
(5)
PLL operation of 1.25GSPS in Mode 1 is used for maximum power consumption measurement only. Please follow the maximum DAC
sample rate (FDAC) guideline in the AC Characteristic Table for proper DAC operation.
8
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Copyright
© 2011, Texas Instruments Incorporated
Product Folder Link(s): DAC34H84


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