PowerPAD

(17)

16

FB

COMP

SS

RT/CLK

PGND

VCC

BOOT

SW

15

14

13

5

6

7

8

1

2

3

4

12

11

10

9

TPS43060

TPS43061

SLVSBP4C – DECEMBER 2012 – REVISED SEPTEMBER 2013

www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

DEVICE INFORMATION

WQFN-16 PACKAGE

(TOP VIEW)

PIN FUNCTIONS

PIN

DESCRIPTION

NAME

NO.

Resistor Timing and External Clock. An external resistor from this pin to the AGND pin programs the switching

RT/CLK

1

frequency between 50 kHz and 1MHz. Driving the pin with an external clock between 300 kHz to 1 MHz will

synchronize the switching frequency to the external clock.

SS

2

Soft-start programming pin. A capacitor between the SS pin and AGND pin sets soft-start time.

Output of the internal transconductance error amplifier. The feedback loop compensation network is connected from

COMP

3

this pin to AGND.

Error amplifier input and feedback pin for voltage regulation. Connect this pin to the center tap of a resistor divider to

FB

4

set the output voltage.

Inductor current sense comparator inverting input pin. This pin is normally connected to the inductor side of the

ISNS-

5

current sense resistor.

Inductor current sense comparator non-inverting input pin. This pin is normally connected to the VIN side of the

ISNS+

6

current sense resistor.

The input supply pin to the IC. Connect VIN to a supply voltage between 4.5 V and 38 V. It is acceptable for the

VIN

7

voltage on the VIN pin to be different from the boost power stage input, ISNS+ and ISNS- pins.

Low side gate driver output. Connect this pin to the gate of the low side N-channel MOSFET. When VIN bias is

LDRV

8

removed, an internal 200 k

Ω resistor pulls LDRV to PGND.

Power ground of the IC. Connect this pin to the source of the low-side MOSFET. PGND should be connected to

PGND

9

AGND via a single point on printed circuit board.

Output of an internal LDO and power supply for internal control circuits and gate drivers. VCC is typically 7.5V for the

VCC

10

TPS43060 and 5.5 V for the TPS43061. Connect a low ESR ceramic capacitor from this pin to PGND. The

recommended capacitance range is from 0.47 µF to 10µF.

Bootstrap capacitor node for high-side MOSFET gate driver. Connect the bootstrap capacitor from this pin to the SW

BOOT

11

pin. For the TPS43060, also connect a bootstrap diode from VCC to BOOT.

Switching node of the boost converter. Connect this pin to the junction of the drain of the low side MOSFET, the

SW

12

source of high side synchronous MOSFET and the inductor.

High side gate driver output. Connect this pin to the gate of the high side synchronous rectifier MOSFET. When VIN

HDRV

13

bias is removed, this pin is connected to SW through an internal 200 k

Ω resistor.

Power good indicator. This pin is an open-drain output. A 10 k

Ω pull-up resistor is recommended between PGOOD

PGOOD

14

and VCC or an external logic supply pin.

2

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