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LM3503 Datasheet(PDF) 4 Page - Texas Instruments |
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LM3503 Datasheet(HTML) 4 Page - Texas Instruments |
4 / 28 page LM3503 SNVS329D – JULY 2005 – REVISED AUGUST 2006 www.ti.com Thermal Properties (3) Junction-to-Ambient Thermal Resistance ( θJA) DSBGA Package 65°C/W WQFN Package 49°C/W (3) The maximum allowable power dissipation is a function of the maximum junction temperature, TJ(MAX), the junction-to-ambient thermal resistance, θJA, and the ambient temperature, TA. See Thermal Properties for the thermal resistance. The maximum allowable power dissipation at any ambient temperature is calculated using: PD(MAX) = (TJ(MAX)–TA)/ θJA. Exceeding the maximum allowable power dissipation will cause excessive die temperature. For more information on this topic, please refer to Application Note 1187(An1187): Leadless Leadframe Package (LLP) and Application Note 1112(AN1112) for DSBGA chip scale package. Electrical Characteristics (1) (2) Limits in standard typeface are for TJ = +25°C. Limits in bold typeface apply over the full operating junction temperature range ( −40°C ≤ TJ ≤ +125°C). Unless otherwise specified,VIN = 2.5V. Symbol Parameter Conditions Min Typ Max Units VIN Input Voltage 2.5 5.5 V IQ Non-Switching Cntrl = 1.6V 0.5 1 mA Switching Fb = 0V, Sw Is Floating 1.9 3 mA Shutdown En1 = En2 = 0V 0.1 3 µA VFb Feedback Voltage Cntrl = 3.5V 0.5 0.55 0.6 V ICL NMOS Power Switch 16, Fb = 0V 250 400 650 Current Limit 25, Fb = 0V 400 600 800 mA 35, Fb = 0V 450 750 1050 44,FB = 0V 450 750 1050 IFb Feedback Pin Output Fb = 0.25V, Cntrl = 1.6V 64 500 nA Bias Current FS Switching Frequency 0.8 1 1.2 MHz RDS(ON) NMOS Power Switch ON ISw = 500 mA (3) Resistance 0.55 1.1 Ω (Figure 3: N1) RPDS(ON) PMOS ON Resistance IPMOS = 20 mA, En1 = 0V, En2 = 1.5V Of VOUT1/VOUT2 Switch 5 10 Ω (Figure 3: P1) RNDS(ON) NMOS ON Resistance INMOS = 20 mA, En1 = 1.5V, En2 = 0V Of VOUT2/Fb Switch 2.5 5 Ω (Figure 3: N2) DMAX Maximum Duty Cycle Fb = 0V 90 95 % ISw Sw Pin Leakage Sw = 42V, En1 = En2 =0V 0.01 5 µA Current(4) IVOUT1(OFF) VOUT1 Pin Leakage VOUT1 = 14V, En1 = En2 = 0V (16) 0.1 3 Current(4) VOUT1 = 23V, En1 = En2 = 0V (25) 0.1 3 µA VOUT1 = 32V, En1 = En2 = 0V (35) 0.1 3 VOUT1 = 42V, En1 = En2 = 0V (44) 0.1 3 IVOUT1(ON) VOUT1 Pin Bias VOUT1 = 14V, En1 = En1 = 1.5V (16) 40 80 Current(4) VOUT1 = 23V, En1 = En2 = 1.5V (25) 50 100 µA VOUT1 = 32V, En1 = En2 = 1.5V (35) 50 100 VOUT1 = 42V, En1 = En2 = 1.5V (44) 85 140 IVOUT2 VOUT2Pin Leakage Fb = En1 = En2 = 0V, VOUT2 = VOUT1 = 42V 0.1 3 µA Current(4) UVP Under-Voltage On Threshold 2.4 2.5 V Protection Off Threshold 2.2 2.3 (1) All voltages are with respect to the potential at the GND pin. (2) Min and Max limits are guaranteed by design, test, or statistical analysis. Typical numbers are not guaranteed, but do represent the most likely norm. (3) NMOS Power On Resistance measured at ISW= 250mA for sixteen voltage version. (4) Current flows into the pin. 4 Submit Documentation Feedback Copyright © 2005–2006, Texas Instruments Incorporated Product Folder Links: LM3503 |
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