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TSB81BA3EZAJ Datasheet(PDF) 9 Page - Texas Instruments |
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TSB81BA3EZAJ Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 58 page  TSB81BA3E www.ti.com SLLS783A – MAY 2009 – REVISED MAY 2010 TERMINAL FUNCTIONS (continued) TERMINAL PFP ZAJ DESCRIPTION PACKAGE PACKAGE NAME TYPE NO. NO. I/O Digital core circuit power terminals. A combination of high-frequency decoupling capacitors near each terminal is suggested, such as paralleled DVDD- 0.1 mF and 0.001 mF. An additional 1-mF capacitor is required for voltage Supply 8, 37, 65, 71 D9, K9, D8 – CORE regulation. These supply terminals are separated from the DVDD-3.3, PLLVDD-CORE, PLLVDD-3.3, and AVDD terminals internal to the device to provide noise isolation. Digital 3.3-V circuit power terminals. A combination of high-frequency decoupling capacitors near each terminal is suggested, such as paralleled 0.1 mF and 0.001 mF. Lower-frequency 10-mF filtering capacitors are also recommended. The DVDD-3.3 terminals must be tied together at a DVDD-3.3 Supply 6, 18, 69, 70 E4, K5, K6 – low-impedance point on the circuit board. These supply terminals are separated from the PLLVDD-CORE, PLLVDD-3.3, DVDD-CORE, and AVDD terminals internal to the device to provide noise isolation. The PLLVDD-3.3, AVDD, and DVDD-3.3 terminals must be tied together with a low dc impedance connection on the circuit board. Link clock. Link-provided 98.304-MHz clock signal to synchronize data LCLK CMOS 7 G2 I transfers from link to the PHY when the PHY-link interface is in the 1394b mode. A bus holder is built into this terminal. Link-on output/Data-strobe-only input for port 2. This terminal may be connected to the link-on input terminal of the LLC through a 1-k Ω resistor if the link-on input is available on the link layer. Data-strobe-only mode for port 2. 1394a-only port 0 enable programming terminal. On hardware reset, this terminal allows the user to select whether port 2 acts like a 1394b bilingual port (terminal at logic 0) or as a 1394a-2000-only port (terminal at logic 1). Programming is accomplished by tying the terminal low through a 1-k Ω or less resistor to enable 1394b bilingual mode or high through a 1-k Ω or less resistor to enable 1394a-2000-only mode. A bus holder is built into this terminal. After hardware reset, this terminal is the link-on output, which notifies the LLC or other power-up logic to power up and become active. The link-on output is a square wave signal with a period of approximately 163 ns (8 PCLK cycles) when active. The link-on output is otherwise driven low, except during hardware reset when it is high impedance. The link-on output is activated if the LLC is inactive (the LPS input inactive or the LCtrl bit cleared) and when one: LKON/DS2 CMOS 2 D2 I/O a. The PHY receives a link-on PHY packet addressed to this node. b. The PEI (port-event interrupt) register bit is 1. c. Any of the CTOI (configuration-timeout interrupt), CPSI (cable-power-status interrupt), or STOI (state-time-out interrupt) register bits is 1 and the RPIE (resuming-port interrupt enable) register bit is also 1. d. The PHY is power-cycled and the power class is 0 through 4. Once activated, the link-on output is active until the LLC becomes active (both the LPS input active and the LCtrl bit set). The PHY also deasserts the link-on output when a bus-reset occurs unless the link-on output is otherwise active because one of the interrupt bits is set (that is, the link-on output is active due solely to the reception of a link-on PHY packet). In the case of power-cycling the PHY, the LKON signal must stop after 167 ms if the preceding conditions have not been met. NOTE: If an interrupt condition exists, which otherwise would cause the link-on output to be activated if the LLC were inactive, then the link-on output is activated when the LLC subsequently becomes inactive. Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Link(s): TSB81BA3E |
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