www.ti.com

FEATURES

DESCRIPTION

TSB43AA82A

TSB43AA82AI

SLLA205 – MAY 2006

(iSphynx II) 1394 Integrated PHY and Link-Layer Controller

for SBP-2 Products and DPP Products

•

Data Transfers:

•

IEEE 1394a-2000 Compliant

– Auto Address Increment of Direct/Indirect

Addressing on Data Transfer (Packetizer)

•

Single 3.3-V Supply

– Automated Header Insert/Strip for DMA

•

Internal 1.8-V Circuit to Reduce Power

Data Transfers

Consumption

– 8-/16-Bit Asynchronous and Synchronous

•

Integrated 400-Mbps Two-Port Physical Layer

DMA I/F With Handshake and Burst Mode

(PHY)

– Supports ATAPI (Ultra-DMA) Mode and

•

Internal Voltage Regulator

SCSI Mode

•

IEEE 1394 Related Functions:

– 8-/16-Bit Data/Address Multiplex

– Automated Read Response for ConfigROM

Microcontroller and 8-/16-Bit Separated

Register Access

Data/Address Bus

– Automated Single Retry Protocol and Split

– Three FIFO Configurations That Support

Transaction Control

High Performance for the DMA and for

•

SBP-2 Related Functions:

Command Exchanges

– Supports Four Initiators by Automated

• Asynchronous Command FIFO: 1512

Transactions and More Can Be Supported

Bytes

Through Firmware.

• Config ROM/LOG FIFO: 504 Bytes

– Automated Management ORB Fetching

• DMA FIFO: 4728 Bytes

– Automated Linked Command ORB Fetching

– Automated PageTable Fetching

– Automated Status Block Transmit

•

Ability to Support Direct Print Protocol (DPP)

Mode

The TSB43AA82A is a high performance 1394 integrated PHY and link layer controller. It is compliant with the

IEEE 1394-1995 and IEEE 1394a-2000 specifications and supports asynchronous transfers.

TSB43AA82A has a generic 16-/8-bit host bus interface. It supports parallel or multiplexed connections to the

microcontroller (MCU) at rates up to 40 MHz.

The TSB43AA82A offers large data transfers with three mutually independent FIFOs: 1) the asynchronous

command FIFO with 1512 Bytes, 2) the DMA FIFO with 4728 bytes and 3) the Config ROM/LOG FIFO with 504

bytes.

The features of the TSB43AA82A support the serial bus protocol 2 (SBP-2). It handles up to four initiators with

the SBP-2 transaction/timer manager. This SBP-2 transaction engine supports fully automated operation request

block (ORB) fetches and fully automated memory page table fetches for both read and write transactions.

Automated responses to other node requests are provided; this includes responding to another node’s read

request to the Config ROM and issuing ack_busy_X for a single retry. Various control registers enable the user

to program IEEE 1394 asynchronous transaction settings. The user can program the number of retries and the

split transaction time-out value by setting the time limit register in the CFR.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Copyright © 2006, Texas Instruments Incorporated

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.