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ADC10040QCIMTX Datasheet(PDF) 8 Page - Texas Instruments |
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ADC10040QCIMTX Datasheet(HTML) 8 Page - Texas Instruments |
8 / 28 page ADC10040 SNAS224M – JULY 2003 – REVISED APRIL 2013 www.ti.com AC Electrical Characteristics Unless otherwise specified, the following specifications apply for VSSA = VSSIO = 0V, VDDA = +3.0V, VDDIO = +2.5V, VIN = 2 VP-P (full scale), STBY = 0V, External VREF = 1.20V, fCLK = 40 MHz, 50% Duty Cycle, CL = 10 pF/pin. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C (1) (2) (3) Symbol Parameter Conditions Min(3) Typ(3) Max(3) Units CLK, DF, STBY, SENSE fCLK1 Maximum Clock Frequency 40 MHz (min) fCLK2 Minimum Clock Frequency 20 MHz tCH Clock High Time 12.5 ns tCL Clock Low Time 12.5 ns tCONV Conversion Latency 6 Cycles T = 25°C 2 3.3 5 ns Data Output Delay after a Rising Clock tOD Edge 1 6 ns tAD Aperture Delay 1 ns tAJ Aperture Jitter 2 ps (RMS) Differential VIN step from ±3V Over Range Recovery Time to 0V to get accurate 1 Clock Cycle conversion tSTBY Standby Mode Exit Cycle 20 Cycles (1) With the test condition for 2 VP-P differential input, the 10-bit LSB is 1.95 mV. (2) Typical figures are at TA = TJ = 25°C and represent most likely parametric norms. Test limits are ensured to TI's AOQL (Average Outgoing Quality Level). (3) Timing specifications are tested at TTL logic levels, VIL = 0.4V for a falling edge, and VIH = 2.4V for a rising edge. 8 Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: ADC10040 |
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