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ADC12138CIMSAX Datasheet(PDF) 8 Page - Texas Instruments

No. de pieza ADC12138CIMSAX
Descripción Electrónicos  ADC12130/ADC12132/ADC12138 Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/Hold
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ADC12138CIMSAX Datasheet(HTML) 8 Page - Texas Instruments

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ADC12130, ADC12132, ADC12138
SNAS098G – MARCH 2000 – REVISED MARCH 2013
www.ti.com
Converter Electrical Characteristics (continued)
The following specifications apply for (V
+ = V
A+ = VD+ = +5V, VREF+ = +4.096V, and fully differential input with fixed 2.048V
common-mode voltage) or (V
+ = V
A+ = VD+ = 3.3V, VREF+ = 2.5V and fully-differential input with fixed 1.250V common-mode
voltage), VREF− = 0V, 12-bit + sign conversion mode
(1), source impedance for analog inputs, V
REF
and V
REF
+ ≤ 25Ω, f
CK = fSK
= 5 MHz, and 10 (tCK) acquisition time unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other
limits TA = TJ = 25°C.
(2)(3)(4)
Units
Parameter
Test Conditions
Typical (5)
Limits (6)
(Limits)
Channel-to-Channel Crosstalk
VIN = 5 VPP, fIN = 40 kHz
−72
dB
MUX Bandwidth
90
kHz
DC and Logic Electrical Characteristics
The following specifications apply for (V
+ = V
A+ = VD+ = +5V, VREF+ = +4.096V, and fully-differential input with fixed 2.048V
common-mode voltage) or (V
+ = V
A+ = VD+ = +3.3V, VREF+ = +2.5V and fully-differential input with fixed 1.250V common-
mode voltage), VREF− = 0V, 12-bit + sign conversion mode
(1), source impedance for analog inputs, V
REF− and VREF+ ≤ 25Ω,
fCK = fSK = 5 MHz, and 10 (tCK) acquisition time unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX;
all other limits TA = TJ = 25°C.
(2) (3) (4)
V+ = VA+ =
V+ = VA+ =
Typical
Units
Parameter
Test Conditions
VD+ = 3.3V
VD+ = 5V
(5)
(Limits)
Limits (6)
Limits (6)
CCLK, CS, CONV, DI, PD AND SCLK INPUT CHARACTERISTICS
VIN(1)
Logical “1” Input Voltage
VA+ = VD+ = V
+ +10%
2.0
2.0
V (min)
VIN(0)
Logical “0” Input Voltage
VA+ = VD+ = V
+ −10%
0.8
0.8
V (max)
IIN(1)
Logical “1” Input Current
VIN = V
+
0.005
1.0
1.0
μA (max)
IIN(0)
Logical `“0” Input Current
VIN = 0V
−0.005
−1.0
−1.0
μA (min)
DO, EOC AND DOR DIGITAL OUTPUT CHARACTERISTICS
VA+ = VD+ = V
+ − 10%,
2.4
2.4
V (min)
IOUT = −360 μA
VOUT(1)
Logical “1” Output Voltage
VA+ = VD+ = V
+ − 10%,
2.9
4.25
V (min)
IOUT = −10 μA
VA+ = VD+ = V
+ − 10%
VOUT(0)
Logical “0” Output Voltage
0.4
0.4
V (max)
IOUT = 1.6 mA
VOUT = 0V
−0.1
−3.0
−3.0
μA (max)
IOUT
TRI-STATE Output Current
VOUT = V
+
−0.1
3.0
3.0
μA (max)
+ISC
Output Short Circuit Source Current
VOUT = 0V
−14
mA
−ISC
Output Short Circuit Sink Current
VOUT = VD+
16
mA
(1)
The “12-Bit Conversion of Offset” and “12-Bit Conversion of Full-Scale” modes are intended to test the functionality of the device.
Therefore, the output data from these modes are not an indication of the accuracy of a conversion result.
(2)
Two on-chip diodes are tied to each analog input through a series resistor as shown below. Input voltage magnitude up to 5V above VA+
or 5V below GND will not damage this device. However, errors in conversion can occur (if these diodes are forward biased by more than
50 mV) if the input voltage magnitude of selected or unselected analog input go above VA+ or below GND by more than 50 mV. As an
example, if VA+ is 4.5 VDC, full-scale input voltage must be ≤4.55 VDC to ensure accurate conversions.
(3)
To ensure accuracy, it is required that the VA+ and VD+ be connected together to the same power supply with separate bypass
capacitors at each V+ pin.
(4)
With the test condition for VREF (VREF+ − VREF−) given as +4.096V, the 12-bit LSB is 1.0 mV. For VREF = 2.5V, the 12-bit LSB is 610 μV.
(5)
Typical figures are at TJ = TA = 25°C and represent most likely parametric norm.
(6)
Tested limits are specified to TI's AOQL (Average Outgoing Quality Level).
8
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Product Folder Links: ADC12130 ADC12132 ADC12138


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