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TLC1551IDWRG4 Datasheet(PDF) 6 Page - Texas Instruments |
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TLC1551IDWRG4 Datasheet(HTML) 6 Page - Texas Instruments |
6 / 17 page TLC1550I, TLC1550M, TLC1551I 10BIT ANALOGTODIGITAL CONVERTERS WITH PARALLEL OUTPUTS SLAS043G − MAY 1991 − REVISED NOVEMBER 2003 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 operating characteristics over recommended operating free-air temperature range with internal clock and minimum sampling time of 4 µs, VDD =VREF+ = 5 V and VREF− = 0 (unless otherwise noted) PARAMETER TEST CONDITIONS TA† MIN TYP‡ MAX UNIT TLC1550I Full range ±0.5 EL Linearity error TLC1551I See Note 3 Full range ±1 LSB EL Linearity error TLC1550M See Note 3 25 °C ±0.5 LSB TLC1550M Full range ±1 TLC1550I Full range ±0.5 EZS Zero-scale error TLC1551I See Notes 2 and 4 Full range ±1 LSB EZS Zero-scale error TLC1550M See Notes 2 and 4 25 °C ±0.5 LSB TLC1550M Full range ±1 TLC1550I Full range ±0.5 EFS Full-scale error TLC1551I See Notes 2 and 4 Full range ±1 LSB EFS Full-scale error TLC1550M See Notes 2 and 4 25 °C ±0.5 LSB TLC1550M Full range ±1 TLC1550I Full range ±0.5 Total unadjusted error TLC1551I See Note 5 Full range ±1 LSB Total unadjusted error TLC1550M See Note 5 25 °C ±1 LSB tc Conversion time fclock(external) = 4.2 MHz or internal clock 6 µs ta(D) Data access time after RD goes low 35 ns tv(D) Data valid time after RD goes high 5 ns tdis(D) Disable time, delay time from RD high to high impedance See Figure 3 30 ns td(EOC) Delay time, RD low to EOC high 0 15 ns † Full range is − 40°C to 85°C for the TL155xI devices and −55°C to 125°C for the TLC1550M. ‡ All typical values are at VDD = 5 V, TA = 25°C. NOTES: 2. Analog input voltages greater than that applied to REF+ convert to all 1s (1111111111), while input voltages less than that applied to REF − convert to all 0s (0000000000). The total unadjusted error may increase as this differential voltage falls below 4.75 V. 3. Linearity error is the difference between the actual analog value at the transition between any two adjacent steps and its ideal value after zero-scale error and full-scale error have been removed. 4. Zero-scale error is the difference between the actual mid-step value and the nominal mid-step value at specified zero scale. Full-scale error is the difference between the actual mid-step value and the nominal mid-step value at specified full scale. 5. Total unadjusted error is the difference between the actual analog value at the transition between any two adjacent steps and its ideal value. It includes contributions from zero-scale error, full-scale error, and linearity error. |
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