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74HC40103N Datasheet(PDF) 7 Page - NXP Semiconductors |
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74HC40103N Datasheet(HTML) 7 Page - NXP Semiconductors |
7 / 25 page 9397 750 13812 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data sheet Rev. 03 — 12 November 2004 7 of 25 Philips Semiconductors 74HC40103 8-bit synchronous binary down counter 8. Functional description 8.1 Function table [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care. [2] Clock connected to CP. Synchronous operation: changes occur on the LOW-to-HIGH CP transition. Jam inputs: MSD = P7, LSD = P0. 9. Limiting values [1] Above 70 °C: P tot derates linearly with 12 mW/K. [2] Above 70 °C: P tot derates linearly with 8 mW/K. Table 4: Function table [1] Control inputs Preset mode Action [2] MR PL PE TE L X X X asynchronous clear to maximum count H L X X asynchronous preset asynchronously H L X synchronous preset on next LOW-to HIGH clock transition H L synchronous count down H synchronous inhibit counter Table 5: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit VCC supply voltage −0.5 +7 V IIK input diode current VI < −0.5 V or VI >VCC + 0.5 V - ±20 mA IOK output diode current VO < −0.5 V or VO >VCC + 0.5 V - ±20 mA IO output source or sink current VO = −0.5 V to VCC + 0.5 V - ±25 mA ICC, IGND VCC or GND current - ±50 mA Tstg storage temperature −65 +150 °C Ptot power dissipation DIP16 package [1] - 750 mW SO16, SSOP16 and TSSOP16 packages [2] - 500 mW |
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