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AD805 Datasheet(PDF) 7 Page - Analog Devices |
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AD805 Datasheet(HTML) 7 Page - Analog Devices |
7 / 12 page AD805 –7– REV. 0 The gain of the loop integrator is small for high jitter frequen- cies, so that larger phase differences between the phase detector inputs are needed to make the internal loop control voltage big enough to tune the range of the VCPS. Large phase errors at high jitter frequencies cannot be tolerated. In this region, the gain of the loop integrator determines the jitter accommodation. Since the gain of the loop integrator declines linearly with frequency, jitter accommodation decreases with increasing jitter frequency. At the highest frequencies, the loop gain is very small and little tuning of the VCPS can be expected. In this case, jitter accommodation is determined by the eye opening of the input data, the static phase error and the residual loop jitter. The jitter accommodation is roughly 0.5 UI in this region. The corner frequency between the declining slope and the flat region is the 3 MHz closed-loop bandwidth of the AD805’s internal delay-locked loop. USING THE AD805 Ground Planes Use of two ground planes, an analog ground plane and a digital ground plane, is recommended. This will isolate noise that may be on the digital ground plane from the analog ground plane. Power Supply Connections Power supply decoupling should take place as close to the IC as possible. This will keep noise that may be on a power supply from affecting circuit performance. Use of a 10 µF tantalum capacitor between V EE and ground is recommended. Use of 0.1 µF ceramic capacitors between IC power supply or substrate pins and either analog or digital ground is recom- mended. Refer to schematic, Figure 12, for advised connections. The ceramic capacitors should be placed as close to the IC pins as possible. Connections from VEE to load resistors for DATAIN, DATAOUT, CLKIN, and CLKOUT signals should be individual, not daisy chained. This will avoid crosstalk on these signals. Transmission Lines Use of 50 Ω transmission lines are recommended for DATAIN, DATAOUT, CLKIN, and CLKOUT signals. Terminations Termination resistors should be used for DATAIN, CLKIN, DATAOUT, and CLKOUT signals. Metal, thick film, 1% tolerance resistors are recommended. Termination resistors for the DATAIN and CLKIN signals should be placed as close as possible to the DATAIN and CLKIN pins. Input Buffer Use of an input buffer, such as a 10H116 Line Receiver IC, is suggested for an application where the DATAIN signals do not come directly from an ECL gate, or where noise immunity on the DATAIN signals is an issue. APPLICATIONS 155.52 MBPS CLOCK RECOVERY AND DATA RETIMING USING AT&T 157-TYPE VHF VOLTAGE-CONTROLLED CRYSTAL OSCILLATOR The AD805 design can be used with any VCXO circuit that has a gain of roughly 1 10 6 rad/volt-sec, a frequency pull range of at least ±50 ppm, a positive slope (a greater VCXO control voltage corresponds to a greater output frequency) and a modulation bandwidth of 500 kHz. These VCXO parameters contribute to overall circuit low frequency jitter tolerance and jitter transfer. The output jitter of the overall circuit is largely determined by the output jitter of the VCXO. The AD805 adds little jitter since it just buffers the VCXO frequency output, adding distortion (duty cycle distortion) of only ±0.5%. Overall circuit jitter bandwidth is determined by the slope of the VCXO output frequency vs. control voltage curve. A greater slope corresponds to a greater jitter bandwidth. Figure 12 shows a schematic of the AD805 in a 155.52 Mbps clock recovery and data retiming application with an AT&T 157-Type VCXO (see insert). Figures 15 and 16 show typical jitter tolerance and jitter transfer curves for the circuit. Note that the 157-Type VCXO control voltage bandwidth (modulation bandwidth) varies with respect to control voltage from 80 kHz to 500 kHz. The low value of this modulation bandwidth causes some jitter peaking when used with the AD805. The limited modulation bandwidth introduces excess phase in the frequency control loop through the VCXO. This causes the frequency control loop to become less damped. Jitter peaking of 1 dB or 2 dB results in the jitter transfer function. The compensation network on the VCXO control voltage between the AD805 and the 157-Type VCXO shown in Figure 12, effectively reduces the high frequency loop gain through the frequency control loop. The addition of this compensation network eliminates jitter peaking. The compensation network 1 k Ω resistor works with the AD805 VCXO CONTROL 1 kΩ output impedance to halve the loop crossover frequency. This avoids excess phase caused by the limited modulation band- width of the 157-Type VCXO. OBSOLETE |
Número de pieza similar - AD805_15 |
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Descripción similar - AD805_15 |
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