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AD9621 Datasheet(PDF) 3 Page - Analog Devices |
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AD9621 Datasheet(HTML) 3 Page - Analog Devices |
3 / 6 page OBSOLETE AD9621 REV. 0 –3– ABSOLUTE MAXIMUM RATINGS 1 Supply Voltages ( ±V S) . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 6 V Common-Mode Input Voltage . . . . . . . . . . . . . . . . . . . . . . ±V S Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V Continuous Output Current 2 . . . . . . . . . . . . . . . . . . . . . 90 mA Operating Temperature Ranges AN, AQ, AR . . . . . . . . . . . . . . . . . . . . . . . . –40 °C to +85°C SQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55 °C to +125°C Storage Temperature Ceramic . . . . . . . . . . . . . . . . . . . . . . . . . . . –65 °C to +150°C Plastic . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65 °C to +125°C Junction Temperature Ceramic 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175 °C Plastic 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150 °C Lead Soldering Temperature (1 minute) 4 . . . . . . . . . . +220 °C NOTES 1Absolute maximum ratings are limiting values to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability is not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability. 2Output is short-circuit protected; for maximum reliability, 90 mA continuous current should not be exceeded. 3Typical thermal impedances (part soldered onto board; no air flow): Ceramic DIP: θ JA = 100°C/W; θJC = 30°C/W Plastic SOIC: θ JA = 125°C/W; θJC = 45°C/W Plastic DIP: θ JA = 90°C/W; θJC = 45°C/W 4Temperature shown is for surface mount devices, mounted by vapor phase soldering. Throughhole devices (ceramic and plastic DIPs) can be soldered at +300 °C for 10 seconds. ORDERING GUIDE Temperature Package Package Model Range Description Option AD9621AN –40 °C to +85°C 8-Pin Plastic DIP N-8 AD9621AQ –40 °C to +85°C 8-Pin Cerdip Q-8 AD9621AR –40 °C to +85°C 8-Pin SOIC R-8 AD9621SQ –55 °C to +125°C 8-Pin Cerdip Q-8 EXPLANATION OF TEST LEVELS Test Level I – 100% production tested. II – 100% production tested at +25 °C, and sample tested at specified temperatures. AC testing of “A” grade devices done on sample basis. III – Sample tested only. IV – Parameter is guaranteed by design and characterization testing. V – Parameter is a typical value only. VI – All devices are 100% production tested at +25 °C. 100% production tested at temperature extremes for extended temperature devices; sample tested at temperature ex- tremes for commercial/industrial devices. –V S 46.5mm – INPUT 46.5mils CB– CB+ –INPUT +INPUT +V S OUTPUT 54mils Chip Layout THEORY OF OPERATION The AD9621 is a wide bandwidth, unity gain stable voltage feedback amplifier. Since its open-loop frequency response fol- lows the conventional 6 dB/octave roll-off, its gain bandwidth product is basically constant. Increasing its closed-loop gain re- sults in a corresponding decrease in small signal bandwidth. The AD9621 typically maintains a 55 degree unity loop gain phase margin. This high margin minimizes the effects of signal and noise peaking. Feedback Resistor Choice At minimum stable gain (+1), the AD9621 provides optimum dynamic performance with RF ≅ 51 Ω. This resistor acts only as a parasitic suppressor against damped RF oscillations that can occur due to lead (input, feedback) inductance and parasitic ca- pacitance. For settling accuracy to 0.1% or less, this resistor should not be required if layout guidelines are closely followed. This value for RF provides the best combination of wide band- width, low parasitic peaking, and fast settling time. When the AD9621 is used in the transimpedance (I-to-V) mode, such as for photo-diode detection, the value for RF and diode capacitance (CI) are usually known. See Figure 1. Gener- ally, the value of RF selected will be in the kΩ range, and a shunt capacitor (CF) across RF will be required to maintain good am- plifier stability. The value of CF required to maintain < 1 dB of peaking can be estimated as: C F ≅ [(2ω οCI RF − 1)ωο 2 R F 2 ] 12 | R F ≥ 1 kΩ where ω o is equal to the unity gain bandwidth product of the amplifier in RAD/sec, and CI is the equivalent total input ca- pacitance at the inverting input. Typically ω o is 700 × 106 RAD/sec (See Open Loop Frequency Response curve). As an example, choosing RF of 10 k Ω and C I of 5 pF, requires CF to be 1.1 pF (Note: CI includes both the source and parasitic circuit capacitance). The bandwidth of the amplifier can be esti- mated using the CF calculated as: f 3 dB ≅ 1.6 2 π R F CF For general voltage gain applications, the amplifier bandwidth can be estimated as: f 3 dB ≅ ωο 1 + R F R G This estimation loses accuracy for gains approaching +2/–1 or lower due to the amplifier’s damping factor. For these “low gain” cases, the bandwidth will actually extend beyond the cal- culated value. See Closed Loop BW plots. As a rule of thumb, capacitor CF will not be required if: R F RG ()C I ≤ NG 4 ωο where NG is the Noise Gain (l + RF/RG) of the circuit. For most voltage gain applications, this should be the case. |
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