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AD568 Datasheet(PDF) 6 Page - Analog Devices |
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AD568 Datasheet(HTML) 6 Page - Analog Devices |
6 / 14 page AD568 REV. A –6– sation capacitor across the 1 k Ω feedback resistor produces opti- mal settling. Lower noise gain can be achieved by connecting RL to IOUT, increasing the DAC output impedance to approximately 200 Ω, and reducing the noise gain to 6 (illustrated in Figure 9). While the output in this configuration will feature improved noise performance, it is somewhat less stable and may suffer from ringing. The compensation capacitance should be in- creased to 7 pF to maintain stability at this reduced gain. 13 16 15 14 24 23 22 21 20 19 18 17 12 11 10 9 8 1 2 3 4 7 6 5 AD568 +15V REFCOM –15V IBPO RL ACOM LCOM SPAN SPAN THCOM VTH IOUT DIGITAL INPUTS 0.2µF 0.1µF 0.1µF 0.1µF –15V +15V ANALOG GND PLANE DIGITAL GND PLANE DIGITAL SUPPLY GROUND 100pF +5V ANALOG OUTPUT ANALOG SUPPLY GROUND 5pF –VS +VS 100 Ω RTH 1k Ω AD840 AMPLIFIER NOISE GAIN: 11 Figure 8. Unipolar Output Buffered 0 to –10.24V 13 16 15 14 24 23 22 21 20 19 18 17 12 11 10 9 8 1 2 3 4 7 6 5 AD568 +15V REFCOM –15V IBPO RL ACOM LCOM SPAN SPAN THCOM VTH IOUT DIGITAL INPUTS 0.2µF 0.1µF 0.1µF 0.1µF –15V +15V ANALOG GND PLANE DIGITAL GND PLANE DIGITAL SUPPLY GROUND 100pF +5V ANALOG OUTPUT ANALOG SUPPLY GROUND 7pF –VS +VS 200 Ω RTH 1k Ω AD840 AMPLIFIER NOISE GAIN: 6 Figure 9. Bipolar Output Buffered ±5.12 V Bipolar Inverting Configuration Figure 9 illustrates the implementation of a +5.12 V to –5.12 V bipolar range, achieved by connecting the bipolar offset current, IBPO, to the summing junction of the external amplifier. Note that since the amplifier is providing an inversion, the full-scale output voltage is –5.12 V, while the bipolar offset voltage (all bits OFF) is +5.12 V at the amplifier output. Noninverting Configuration If a positive full-scale output voltage is required, it can be imple- mented using the AD568 in the unbuffered voltage output mode followed by the AD840 in a noninverting configuration (Figure 10). The noise gain of this topology is 10, requiring only 5 pF across the feedback resistor to optimize settling. 13 16 15 14 24 23 22 21 20 19 18 17 12 11 10 9 8 1 2 3 4 7 6 5 AD568 +15V REFCOM –15V IBPO RL ACOM LCOM SPAN SPAN THCOM VTH IOUT DIGITAL INPUTS 0.2µF 0.1µF 0.1µF 0.1µF –15V +15V ANALOG GND PLANE DIGITAL SUPPLY GROUND 100pF +5V ANALOG OUTPUT ANALOG SUPPLY GROUND 5pF –VS +VS 111 Ω RTH 1k Ω AD840 AMPLIFIER NOISE GAIN: 10 DIGITAL GND PLANE Figure 10. Unipolar Output Buffered 0 V to +10.24 V Guidelines for Using the AD568 The designer who seeks to combine high speed with high preci- sion faces a challenging design environment. Where tens of milliamperes are involved, fractions of an ohm of misplaced impedance can generate several LSBs of error. Increasing bandwidths make formerly negligible parasitic capacitances and inductances significant. As system performance reaches and ex- ceeds that of the measurement equipment, time-honored test methods may no longer be trustworthy. The DAC’s placement on the boundary between the analog and digital domains intro- duces additional concerns. Proper RF techniques must be used in board design, device selection, supply bypassing, grounding, and measurement if optimal performance is to be realized. The AD568 has been configured to be relatively easy to use, even in some of the more treacherous applications. The device charac- teristics shown in this data sheet are readily achievable if proper attention is paid to the details. Since a solid understanding of the circuit involved is one of the designer’s best weapons against the difficulties of RF design, the following sections provide illus- trations, explanations, examples, and suggestions to facilitate successful design with the AD568. Current Output vs. Voltage Output As indicated in Figures 3 through 10, the AD568 has been designed to operate in several different modes depending on the external circuit configuration. While these modes may be categorized by many different schemes, one of the most impor- tant distinctions to be made is whether the DAC is to be used to generate an output voltage or an output current. In the current output mode, the DAC output (Pin 20) is tied to some type of summing junction, and the current flowing from the DAC into this summing junction is sensed (e.g., Figures 8 and 9). In this |
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