AD5372/AD5373

Rev. C | Page 10 of 28

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

VOUT27

SIGGND3

VOUT28

VOUT29

VOUT30

VOUT31

NC

NC

NC

NC

NC

NC

NC

BUSY

RESET

SIGGND0

VOUT3

VOUT2

VOUT1

VOUT0

VREF0

VOUT23

VOUT22

VOUT21

VOUT20

SIGGND2

VOUT19

VOUT4

VOUT5

2

3

4

7

6

5

1

8

9

10

12

13

14

15

16

11

47

46

45

42

43

44

48

41

40

39

37

36

35

34

33

38

NC = NO CONNECT

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

AD5372/AD5373

TOP VIEW

(Not to Scale)

PIN 1

INDICATOR

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

RESET

BUSY

VOUT27

SIGGND3

VOUT28

VOUT29

VOUT30

VOUT31

NC

NC

NC

NC

NC

NC

NC

VOUT5

VOUT4

SIGGND0

VOUT3

VOUT2

VOUT1

VOUT0

VREF0

VOUT23

VOUT22

VOUT21

VOUT20

SIGGND2

VOUT19

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

TOP VIEW

AD5372/AD5373

(Not to Scale)

NOTES

1. NC = NO CONNECT.

2. THE LEAD FRAME CHIP SCALE PACKAGE (LFCSP) HAS AN EXPOSED PAD

PIN 1

INDICATOR

Figure 7. 64-Lead LFCSP Pin Configuration

Figure 8. 64-Lead LQFP Pin Configuration

Table 6. Pin Function Descriptions

Pin No.

Mnemonic

Description

0

EPAD

Exposed Pad. The lead frame chip scale package (LFCSP) has an exposed pad on the

1

RESET

Digital Reset Input.

2

BUSY

Digital Input/Open-Drain Output. BUSY is open drain when an output. See the BUSY and

LDAC Functions section for more information.

42 to 45, 47 to 50, 21 to 24,

26 to 33, 37 to 40, 60 to 62,

3, 5 to 8

VOUT0 to

VOUT31

DAC Outputs. Buffered analog outputs for each of the 32 DAC channels. Each analog output is

capable of driving an output load of 10 kΩ to ground. Typical output impedance of these

amplifiers is 0.5 Ω.

4

SIGGND3

Reference Ground for DAC 24 to DAC 31. VOUT24 to VOUT31 are referenced to this voltage.

9 to 15, 19, 20

NC

No Connect.

16, 35

Positive Analog Power Supply; 9 V to 16.5 V for specified performance. These pins should be

decoupled with 0.1 μF ceramic capacitors and 10 μF capacitors.

17, 36

Negative Analog Power Supply; −16.5 V to −8 V for specified performance. These pins should

be decoupled with 0.1 μF ceramic capacitors and 10 μF capacitors.

18

VREF1

Reference Input for DAC 8 to DAC 31. This reference voltage is referred to AGND.

25

SIGGND1

Reference Ground for DAC 8 to DAC 15. VOUT8 to VOUT15 are referenced to this voltage.

34

SIGGND2

Reference Ground for DAC 16 to DAC 23. VOUT16 to VOUT23 are referenced to this voltage.

41

VREF0

Reference Input for DAC 0 to DAC 7. This reference voltage is referred to AGND.

46

SIGGND0

Reference Ground for DAC 0 to DAC 7. VOUT0 to VOUT7 are referenced to this voltage.

51, 58

DGND

Ground for All Digital Circuitry. The DGND pins should be connected to the DGND plane.

52, 57

Logic Power Supply; 2.5 V to 5.5 V. These pins should be decoupled with 0.1 μF ceramic

capacitors and 10 μF capacitors.

53

SYNC

Active Low Input. This is the frame synchronization signal for the serial interface.

54

SCLK

Serial Clock Input. Data is clocked into the shift register on the falling edge of SCLK. This pin

operates at clock speeds up to 50 MHz.

55

SDI

Serial Data Input. Data must be valid on the falling edge of SCLK.