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AD5429 Datasheet(PDF) 4 Page - Analog Devices

No. de pieza AD5429
Descripción Electrónicos  Dual 8-/10-/12-Bit, High Bandwidth, Multiplying DACs with Serial Interface
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Fabricante Electrónico  AD [Analog Devices]
Página de inicio  http://www.analog.com
Logo AD - Analog Devices

AD5429 Datasheet(HTML) 4 Page - Analog Devices

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Data Sheet
AD5429/AD5439/AD5449
Rev. E | Page 3 of 28
SPECIFICATIONS
VDD = 2.5 V to 5.5 V, VREF = 10 V, IOUT2 = 0 V. Temperature range for Y version: −40°C to +125°C. All specifications TMIN to TMAX, unless
otherwise noted. DC performance is measured with the OP177, and ac performance is measured with the AD8038, unless otherwise noted.
Table 1.
Parameter1
Min
Typ
Max
Unit
Conditions
STATIC PERFORMANCE
AD5429
Resolution
8
Bits
Relative Accuracy
±0.5
LSB
Differential Nonlinearity
±1
LSB
Guaranteed monotonic
AD5439
Resolution
10
Bits
Relative Accuracy
±0.5
LSB
Differential Nonlinearity
±1
LSB
Guaranteed monotonic
AD5449
Resolution
12
Bits
Relative Accuracy
±1
LSB
Differential Nonlinearity
−1/+2
LSB
Guaranteed monotonic
Gain Error
±25
mV
Gain Error Temperature
Coefficient
±5
ppm FSR/°C
Output Leakage Current
±5
nA
Data = 0x0000, TA = 25°C, IOUT1
±15
nA
Data = 0x0000, IOUT1
REFERENCE INPUT
Reference Input Range
±10
V
VREFA, VREFB Input Resistance
9
11
13
kΩ
Input resistance temperature coefficient = −50 ppm/°C
VREFA-to-VREFB Input Resistance
Mismatch
1.6
2.5
%
Typical = 25°C, maximum = 125°C
Input Capacitance
Code 0
3.5
pF
Code 4095
3.5
pF
DIGITAL INPUTS/OUTPUT
Input High Voltage, VIH
1.7
V
VDD = 3.6 V to 5.5 V
1.7
V
VDD = 2.5 V to 3.6 V
Input Low Voltage, VIL
0.8
V
VDD = 2.7 V to 5.5 V
0.7
V
VDD = 2.5 V to 2.7 V
Output High Voltage, VOH
VDD − 1
V
VDD = 4.5 V to 5.5 V, ISOURCE = 200 µA
VDD − 0.5
V
VDD = 2.5 V to 3.6 V, ISOURCE = 200 µA
Output Low Voltage, VOL
0.4
V
VDD = 4.5 V to 5.5 V, ISINK = 200 µA
0.4
V
VDD = 2.5 V to 3.6 V, ISINK = 200 µA
Input Leakage Current, IIL
1
µA
Input Capacitance
4
10
pF
DYNAMIC PERFORMANCE
Reference-Multiplying Bandwidth
10
MHz
VREF = ±3.5 V p-p, DAC loaded all 1s
Output Voltage Settling Time
RLOAD = 100 Ω, CLOAD = 15 pF, VREF = 10 V,
DAC latch alternately loaded with 0s and 1s
Measured to ±1 mV of FS
80
120
ns
Measured to ±4 mV of FS
35
70
ns
Measured to ±16 mV of FS
30
60
ns
Digital Delay
20
40
ns
Digital-to-Analog Glitch Impulse
3
nV-sec
1 LSB change around major carry, VREF = 0 V


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