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AD6623 Datasheet(PDF) 6 Page - Analog Devices |
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AD6623 Datasheet(HTML) 6 Page - Analog Devices |
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6 / 48 page  REV. A –6– AD6623 MICROPROCESSOR PORT TIMING CHARACTERISTICS1, 2 Test AD6623AS Parameter (Conditions) Temp Level Min Typ Max Unit MICROPROCESSOR PORT, MODE INM (MODE = 0) MODE INM Write Timing: tSC Control 3 to ↑CLK Setup Time Full IV 4.5 ns tHC Control 3 to ↑CLK Hold Time Full IV 2.0 ns tHWR WR(RW) to RDY(DTACK) Hold Time Full IV 8.0 ns tSAM Address/Data to WR(RW) Setup Time Full IV 3.0 ns tHAM Address/Data to RDY( DTACK) Hold Time Full IV 2.0 ns tDRDY WR(RW) to RDY(DTACK) Delay Full IV 4.0 ns tACC WR(RW) to RDY(DTACK) High Delay Full IV 4 × t CLK 5 × t CLK 9 × t CLK ns MODE INM Read Timing: tSC Control 3 to ↑CLK Setup Time Full IV 4.5 ns tHC Control 3 to ↑CLK Hold Time Full IV 2.0 ns tSAM Address to RD(DS) Setup Time Full IV 3.0 ns tHAM Address to Data Hold Time Full IV 2.0 ns tZOZ Data Three-State Delay Full IV ns tDD RDY( DTACK) to Data Delay Full IV ns tDRDY RD(DS) to RDY(DTACK) Delay Full IV 4.0 ns tACC RD(DS) to RDY(DTACK) High Delay Full IV 8 × t CLK 10 × t CLK 13 × t CLK ns MICROPROCESSOR PORT, MOTOROLA (MODE = 1) MODE MNM Write Timing: tSC Control 3 to ↑CLK Setup Time Full IV 4.5 ns tHC Control 3 to ↑CLK Hold Time Full IV 2.0 ns tHDS DS(RD) to DTACK(RDY) Hold Time Full IV 8.0 ns tHRW RW( WR) to DTACK(RDY) Hold Time Full IV 8.0 ns tSAM Address/Data to RW( WR) Setup Time Full IV 3.0 ns tHAM Address/Data to RW( WR) Hold Time Full IV 2.0 ns tDDTACK DS(RD) to DTACK(RDY) Delay ns tACC RW( WR) to DTACK(RDY) Low Delay Full IV 4 × tCLK 5 × tCLK 9 × tCLK ns MODE MNM Read Timing: tSC Control 3 to ↑CLK Setup Time Full IV 4.0 ns tHC Control 3 to ↑CLK Hold Time Full IV 2.0 ns tHDS DS(RD) to DTACK(RDY) Hold Time Full IV 8.0 ns tSAM Address to DS(RD) Setup Time Full IV 3.0 ns tHAM Address to Data Hold Time Full IV 2.0 ns tZD Data Three-State Delay Full IV ns tDD DTACK(RDY) to Data Delay Full IV ns tDDTACK DS(RD) to DTACK(RDY) Delay Full IV ns tACC DS(RD) to DTACK(RDY) Low Delay Full IV 8 × t CLK 10 × t CLK 13 × t CLK ns NOTES 1All Timing Specifications valid over VDD range of 2.375 V to 2.675 V and VDDIO range of 3.0 V to 3.6 V. 2C LOAD = 40 pF on all outputs (unless otherwise specified). 3Specification pertains to control signals: RW, ( WR), DS, (RD), CS. Specifications subject to change without notice. |
Número de pieza similar - AD6623_15 |
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Descripción similar - AD6623_15 |
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