AD7767

Rev. C | Page 6 of

24

TIMING DIAGRAMS

MCLK

1

DRDY

8 × n

8 × n

1

Figure 2. DRDY vs. MCLK Timing Diagram, n = 1 for AD7767 (Decimate by 8), n = 2 for AD7767-1 (Decimate by 16), n = 4 for AD7767-2 (Decimate by 32)

DRDY

CS

SCLK

SDO

D22

MSB

D21

D20

D1

LSB

1

23

Figure 3. Serial Timing Diagram, Reading Data Using CS

CS = 0

SCLK

SDO

DATA

INVALID

MSB

D22

D21

D20

D1

LSB

DATA

INVALID

DRDY

1

23

24

Figure 4. Serial Timing Diagram, Reading Data Setting CS Logic Low