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CD4015 Datasheet(PDF) 3 Page - Intersil Corporation |
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CD4015 Datasheet(HTML) 3 Page - Intersil Corporation |
3 / 3 page 3 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with- out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Die Characteristics DIE DIMENSIONS: (2032 µm x 2489µm x 533µm ±25.4µm) 80 x 98 x 21mils ±1mil METALLIZATION: Type: Al Thickness: 12.5k Å ±1.5kÅ SUBSTRATE POTENTIAL: Leave Floating or Tie to VDD; Bond Pad #16 (VDD) First BACKSIDE FINISH: Silicon PASSIVATION: Type: Phosphorus Doped Silox (SiO2) Thickness: 13k Å ±2.6kÅ WORST CASE CURRENT DENSITY: < 2.0e5 A/cm2 TRANSISTOR COUNT: 60 PROCESS: Bulk CMOS Metallization Mask Layout CD4015BT 13 3 14 15 12 11 10 2 1 16 4 5 6 7 8 9 98mils 80mils CD4015BT |
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