AD9510_15 datasheet(3/56 Pages) AD

No. de pieza	AD9510

Descripción Electrónicos	1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs

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Fabricante Electrónico	AD [Analog Devices]

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Data Sheet

AD9510

Rev. B | Page 3 of 56

5/05—Rev. 0 to Rev. A

Changes to Features ..........................................................................1

Changes to Table 1 and Table 2 .......................................................5

Changes to Table 4 ............................................................................8

Changes to Table 5 ............................................................................9

Changes to Table 6 ..........................................................................14

Changes to Table 8 and Table 9 .....................................................15

Changes to Table 11 ........................................................................16

Changes to Table 13 ........................................................................20

Changes to Figure 7 and Figure 10 ...............................................22

Changes to Figure 19 to Figure 23 ................................................24

Changes to Figure 30 and Figure 31 .............................................26

Changes to Figure 32 ......................................................................27

Changes to Figure 33 ......................................................................28

Changes to VCO/VCXO Clock Input—CLK2 Section..............29

Changes to A and B Counters Section .........................................30

Changes to PLL Digital Lock Detect Section ..............................31

Changes to PLL Analog Lock Detect Section..............................32

Changes to Loss of Reference Section ..........................................32

Changes to FUNCTION Pin Section ...........................................33

Changes to RESETB: 58h<6:5> = 00b (Default) Section ...........33

Changes to SYNCB: 58h<6:5> = 01b Section..............................33

Changes to CLK1 and CLK2 Clock Inputs Section....................33

Changes to Calculating the Delay Section...................................38

Changes to Soft Reset via the Serial Port Section.......................41

Changes to Multichip Synchronization Section..........................41

Changes to Serial Control Port Section .......................................42

Changes to Serial Control Port Pin Descriptions Section .........42

Changes to General Operation of Serial

Control Port Section.......................................................................42

Added Framing a Communication Cycle with CSB Section ....42

Added Communication Cycle—Instruction Plus

Data Section.....................................................................................42

Changes to Write Section...............................................................42

Changes to Read Section................................................................42

Changes to The Instruction Word (16 Bits) Section ..................43

Changes to Table 20 ........................................................................43

Changes to MSB/LSB First Transfers Section .............................43

Changes to Table 21 ........................................................................44

Added Figure 52; Renumbered Sequentially...............................45

Changes to Table 23 ........................................................................46

Changes to Table 24 ........................................................................49

Changes to Using the AD9510 Outputs for ADC Clock

Applications .....................................................................................57

4/05—Revision 0: Initial Version

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